Overview
Self-checking tests are tests or programs that validate their own execution results rather than relying solely on external inspection. In the cited RISC-V verification flow, ImperasTS suites are described as self-checking and as automatically comparing results against a reference model, which helps uncover subtle design issues and accelerate coverage closure. [C1]
Role in RISC-V Verification
Self-checking tests appear as part of a hybrid RISC-V verification methodology that combines constrained-random and directed stimulus. STING is described as a bare-metal functional verification tool for RISC-V that generates portable, self-checking programs. These programs can run across simulation, emulation, FPGA prototypes, and silicon, supporting both constrained-random and directed stimulus. [C2]
Directed ImperasTS suites provide structured validation and feature coverage. The evidence states that ImperasTS suites self-check and automatically compare results against a reference model, making them useful for finding subtle design issues while accelerating coverage closure. [C1]
Debug and Comparison
The evidence distinguishes self-checking tests from lock-step compare, but describes them as complementary. Combining architecturally self-checking tests with lock-step compare in ImperasDV enables engineers to identify mismatches immediately, simplifying root-cause analysis. [C3]
Lock-step compare is defined in the evidence as running RTL and a golden reference model in parallel and comparing results at instruction retirement for early bug detection. [C4]
Portability and Lifecycle Use
The evidence emphasizes portability: tests can be used across simulation, emulation such as ZeBu, FPGA prototyping such as HAPS, and silicon. This portability supports a shift-left methodology in which tests developed during RTL bring-up remain valuable through later validation stages and even in silicon. [C5]
Benefits Identified in the Evidence
Self-checking tests contribute to several verification outcomes in the cited methodology:
- Faster coverage closure: random stimulus can expose unexpected behavior, while directed suites such as ImperasTS provide precise tests for coverage convergence. [C6]
- Improved debug efficiency: self-checking tests combined with lock-step compare help identify mismatches immediately. [C3]
- Reproducibility: logged seeds and directed reruns support reproducibility across regression cycles. [C7]
- Portability: self-checking programs and tests can be reused across multiple execution platforms, including simulation, emulation, FPGA prototypes, and silicon. [C2][C5]
Related RISC-V Test-Suite Examples
The evidence lists several ImperasTS suite categories:
- TS-ISA: architectural validation tests similar to compliance suites, included with ImperasDV licences. [C8]
- TS-VECT: targeted test suites for vector extensions. [C8]
- TS-MMU / PMP / ePMP: directed suites for virtual memory management and memory protection features. [C8]