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Lock-Step Compare

Concept

Lock-Step Compare is a RISC-V verification technique that runs RTL and a golden reference model in parallel and compares their results at instruction retirement to detect bugs early.

First seen 5/25/2026
Last seen 5/26/2026
Evidence 2 chunks
Wiki v1

WIKI

Definition

Lock-Step Compare is a processor verification technique in which the RTL implementation and a golden reference model are run in parallel, with results compared at instruction retirement. Its purpose is early bug detection by identifying behavioral mismatches as soon as they appear.

Role in RISC-V verification

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RELATIONSHIPS

2 connections
ImperasDV ← implements 98% 2e
ImperasDV enables lock-step comparison of RTL against a golden reference model at instruction retirement.
Golden Reference Model uses → 98% 2e
Lock-step compare runs RTL and a golden reference model in parallel to detect mismatches at instruction retirement.

CITATIONS

3 sources
3 citations — click to collapse
[1] Lock-Step Compare definition source
[2] ImperasDV enables lock-step comparison source
[3] Lock-Step Compare improves debug efficiency with ImperasDV source