Cache Coherence Conflicts
ConceptCache coherence conflicts are multi-core cache issues in which multiple accesses to the same cache line can lead to stale data, corruption, or stalls when coherence is not enforced correctly. In the provided RISC-V verification context, they are identified as bugs that constrained-random stimulus, such as STING-generated tests, has exposed.
First seen 5/26/2026
Last seen 5/26/2026
Evidence 2 chunks
Wiki v1
WIKI
Definition
Cache coherence conflicts are issues in multi-core caches where multiple accesses to the same cache line cause stale data, corruption, or stalls if coherence is not enforced correctly. [C1]
Technical context
NEIGHBORHOOD
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1 connectionsSTING has exposed cache coherence conflicts during verification runs.
LINKED ENTITIES
3 linksSTING can_expose The evidence states that STING-generated constrained-random stimulus has exposed cache coherence conflicts in practice.
Constrained-Random Testing verification_approach_for The evidence states that constrained-random stimulus is used to uncover unexpected behaviours and that STING has exposed cache coherence conflicts.
RISC-V Processor Verification verification_context The evidence discusses cache coherence conflicts in the context of RISC-V design verification and STING-generated RISC-V tests.
CITATIONS
5 sources5 citations — click to expand
[1] Cache coherence conflicts are multi-core cache issues where multiple accesses to the same line can cause stale data, corruption, or stalls if coherence is not enforced correctly. source
[2] RISC-V processor verification is complex because of the ISA's modular design and optional extensions, and comprehensive coverage requires multiple verification/comparison methodologies and stimulus techniques. source
[3] STING has exposed cache coherence conflicts in practice, along with issues such as page-table-walk deadlocks, mishandling of fence.i, and floating-point NaN quirks. source
[4] Random testing can uncover unanticipated behaviours but may leave gaps; directed tests provide structure but may miss subtle corner cases, so the evidence recommends combining constrained-random stimulus with directed suites. source
[5] STING is a bare-metal RISC-V verification tool that generates constrained-random and directed tests, with portable, architecturally self-checking programs across simulation, emulation, FPGA prototypes, and silicon. source