Constrained-Random Testing

Concept

Constrained-random testing is a stimulus-generation technique used in RISC-V processor verification to explore broad design state spaces and surface unexpected behaviours that directed tests might miss. Evidence shows it is most effective when combined with directed test suites, functional coverage analysis, reference-model comparison, and portable execution across simulation, emulation, prototyping, and silicon.

First seen 5/25/2026

Last seen 8/2/2026

Evidence 5 chunks

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Overview

Constrained-random testing is a stimulus-generation technique widely used in functional verification of digital designs. In RISC-V processor verification specifically, it provides breadth: random stimulus can explore broad state spaces and uncover unanticipated behaviours ^[1]. However, evidence indicates that random testing alone can leave verification gaps, especially for features such as privilege-mode transitions, page-table walks, and memory protection. A stronger strategy combines constrained-random stimulus with directed suites for targeted closure and compliance-oriented validation [b73d6860-3caf-4eb7-811e-eda1693f60f3, e79e3ecb-a829-4ced-b719-7d329fb97e3b].

Role in RISC-V Verification

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RELATIONSHIPS

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Functional Verification ← uses 88% 1e

Functional verification uses constrained-random testing as a technique for stimulus generation, which is introduced after mastering testbench connectivity.

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Functional Verification USES Extracted graph relationship

CITATIONS

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[1] Constrained-random testing explores broad state spaces and uncovers unanticipated behaviours, but random stimulus alone leaves verification gaps for features such as privilege-mode transitions, page-table walks, and memory protection. RISC-V Test Generation: Random, Directed, Coverage

[2] STING is a bare-metal, software-driven RISC-V generator producing C++-based random streams and ASM-style directed tests, with stimulus graphs for scheduling control. RISC-V Test Generation: Random, Directed, Coverage

[3] STING-generated programs are portable across simulation, ZeBu emulation, HAPS FPGA prototypes, and silicon, and are architecturally self-checking. RISC-V Test Generation: Random, Directed, Coverage

[4] STING-generated constrained-random stimulus has uncovered deadlocks in page-table walks, mishandling of the fence.i instruction, floating-point NaN quirks, and cache-coherence conflicts. RISC-V Test Generation: Random, Directed, Coverage

[5] A hybrid verification flow combines constrained-random sweeps (STING) with functional coverage analysis (ImperasFC) and directed suites (ImperasTS) to close coverage gaps, integrated with Verdi and VCS for debug. RISC-V Test Generation: Random, Directed, Coverage

[6] ImperasDV enables lock-step comparison of RTL against a golden reference model at instruction retirement for early bug detection. RISC-V Test Generation: Random, Directed, Coverage

[7] Portability of STING-generated tests across simulation, emulation, prototyping, and silicon enables a shift-left verification methodology. RISC-V Test Generation: Random, Directed, Coverage

[8] SystemVerilog verification methodology teaches interfaces, modports, and clocking blocks before introducing constrained-random stimulus, to ensure race-free testbench-to-DUT communication. Debugging Intermittent SystemVerilog randomize() Failures