Constrained-Random Testing

Concept

Constrained-random testing is a stimulus technique used in RISC-V processor verification to explore broad design state spaces and uncover unexpected behaviours. Evidence shows it is most effective when combined with directed test suites, coverage analysis, reference-model comparison, and portable execution across simulation, emulation, prototyping, and silicon.

First seen 5/25/2026

Last seen 5/25/2026

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Overview

Constrained-random testing is used in RISC-V processor verification to provide breadth: random stimulus can explore broad state spaces and uncover unanticipated behaviours. However, evidence indicates that random testing alone can leave verification gaps, especially for features such as privilege-mode transitions, page-table walks, and memory protection. A stronger strategy combines constrained-random stimulus with directed suites for targeted closure and compliance-oriented validation.

Role in RISC-V Verification

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LINKED ENTITIES

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STING GENERATES Extracted graph relationship

Hybrid Verification Methodology COMBINES Extracted graph relationship

CITATIONS

12 sources

12 citations — click to expand

[1] RISC-V processor verification is complicated by the ISA’s modular design and optional extensions, and comprehensive coverage requires multiple stimulus techniques. RISC-V test generation: random, directed, coverage

[2] Random testing explores broad state spaces and can uncover unanticipated behaviours, but random stimulus alone may leave gaps. RISC-V test generation: random, directed, coverage

[3] Privilege-mode transitions, page-table walks, and memory protection may not be fully exercised by random generation alone. RISC-V test generation: random, directed, coverage

[4] STING is a bare-metal, software-driven RISC-V generator that produces C++-based random streams and ASM-style directed tests. RISC-V test generation: random, directed, coverage

[5] STING-generated programs are portable across simulation, ZeBu emulation, HAPS FPGA prototypes, and silicon, and are architecturally self-checking. RISC-V test generation: random, directed, coverage

[6] STING is useful for stressing privilege levels, memory protection, CSRs, and hypervisor extensions. RISC-V test generation: random, directed, coverage

[7] STING has exposed issues including page-table-walk deadlocks, fence.i mishandling, floating-point NaN quirks, and cache-coherence conflicts. RISC-V test generation: random, directed, coverage

[8] A hybrid verification flow combines constrained-random sweeps, functional coverage analysis, and directed tests for coverage closure. RISC-V test generation: random, directed, coverage

[9] ImperasTS suites target architectural validation, vector extensions, virtual memory, PMP, and ePMP features. RISC-V test generation: random, directed, coverage

[10] ImperasFC generates SystemVerilog coverage models from the ISA specification, results can be viewed in Verdi, and failing cases can be replayed in VCS. RISC-V test generation: random, directed, coverage

[11] ImperasDV enables lock-step comparison against a reference model at instruction retirement. RISC-V test generation: random, directed, coverage

[12] Portability of generated tests across simulation, emulation, prototyping, and silicon enables shift-left verification. RISC-V test generation: random, directed, coverage