Definition

Cache coherence conflicts are issues in multi-core caches where multiple accesses to the same cache line cause stale data, corruption, or stalls if coherence is not enforced correctly. [C1]

Technical context

In a multi-core cache environment, the conflict arises around shared cache-line access. The provided evidence identifies three possible outcomes when coherence is not correctly enforced:

• Stale data: a core may observe an outdated value for a cache line. [C1]
• Corruption: conflicting accesses may lead to incorrect data state. [C1]
• Stalls: the system may fail to make expected progress while resolving, or failing to resolve, the conflicting accesses. [C1]

Verification relevance

Cache coherence conflicts appear in the evidence as a class of bug relevant to RISC-V processor verification. The evidence states that RISC-V processor verification is complex because the ISA is modular and has many optional extensions, and that comprehensive coverage typically requires more than one verification or comparison methodology and more than one stimulus technique. [C2]

The evidence specifically reports that STING-generated constrained-random stimulus has exposed cache coherence conflicts in practice, alongside other issues such as page-table-walk deadlocks, mishandling of fence.i, and floating-point NaN quirks. [C3]

Testing approach indicated by the evidence

The evidence positions constrained-random testing as important for finding unexpected behaviours. It states that random stimuli are effective at uncovering unanticipated behaviours, but that random testing alone can leave verification gaps. Directed tests can validate specific features systematically, but may miss subtle corner cases. The recommended approach in the evidence is therefore a combination of constrained-random stimulus for breadth and directed suites for precision. [C4]

For cache coherence conflicts specifically, the evidence supports treating them as a target for stress-oriented verification in multi-core cache scenarios, especially where shared-line interactions may expose stale data, corruption, or stalls. [C1][C3]

Related verification tooling

The evidence names STING as a bare-metal functional verification tool for RISC-V that generates constrained-random and directed tests. It also states that STING-generated programs are portable across simulation, emulation, FPGA prototypes, and silicon, and that they are architecturally self-checking. [C5]

Because cache coherence conflicts are listed among issues that STING has exposed in practice, STING is directly relevant to verification flows that need to uncover such multi-core cache behaviours. [C3]