HAPS

Tool

HAPS is identified in the provided evidence as an FPGA prototyping target used in RISC-V verification flows where tests are intended to remain portable across simulation, emulation, FPGA prototypes, and silicon.

First seen 5/25/2026

Last seen 5/26/2026

Evidence 3 chunks

Wiki v1

WIKI

Overview

HAPS is referenced as an FPGA prototyping platform in a RISC-V verification methodology. In the cited flow, tests are described as portable across multiple execution targets: simulation, emulation using ZeBu, FPGA prototyping using HAPS, and silicon. This portability is presented as enabling a shift-left methodology in which tests created during RTL bring-up remain useful in later validation stages and on silicon.[C1]

Role in Verification Flows

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NEIGHBORHOOD

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RELATIONSHIPS

1 connections

STING uses → 95% 2e

STING-generated portable tests are executed on HAPS FPGA prototyping platform.

LINKED ENTITIES

2 links

Synopsys DEVELOPED_BY Extracted graph relationship

ZeBu CO_MENTIONED_VERIFICATION_TARGET The evidence lists ZeBu emulation and HAPS FPGA prototyping together as targets across which RISC-V verification tests are portable.

CITATIONS

2 sources

2 citations — click to collapse

[1] HAPS is referenced as an FPGA prototyping target in a RISC-V verification flow where tests are portable across simulation, ZeBu emulation, HAPS FPGA prototyping, and silicon. source

[2] Portable tests and self-checking programs are described as supporting execution across simulation, emulation, FPGA prototypes, and silicon, including constrained-random and directed stimulus. source