Overview

HAPS is referenced as an FPGA prototyping platform in a RISC-V verification methodology. In the cited flow, tests are described as portable across multiple execution targets: simulation, emulation using ZeBu, FPGA prototyping using HAPS, and silicon. This portability is presented as enabling a shift-left methodology in which tests created during RTL bring-up remain useful in later validation stages and on silicon.[C1]

Role in Verification Flows

Within the described RISC-V verification lifecycle, HAPS appears as one target in a broader portable-test strategy. The evidence states that portable, self-checking programs can run across simulation, emulation, FPGA prototypes, and silicon, supporting constrained-random and directed stimulus.[C2]

The methodology emphasizes that portability across these environments helps verification teams reuse tests through multiple stages of validation rather than creating separate test collateral for each platform.[C1]

Relationship to Synopsys

The provided entity graph lists Synopsys as the organization associated with HAPS through a DEVELOPED_BY relationship.