Portable Stimulus

Concept

Portable Stimulus, in the cited RISC-V verification flow, refers to generated tests that can execute across multiple validation platforms such as simulation, emulation, FPGA prototyping, and silicon. The evidence presents STING-generated C++ random streams and ASM-style directed tests as portable, architecturally self-checking stimulus that supports shift-left verification and reuse across the verification lifecycle.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 3 chunks

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WIKI

Overview

Portable Stimulus is a verification concept in which generated tests remain usable across multiple execution targets. In the RISC-V verification flow described in the evidence, portable stimulus is illustrated by STING-generated C++ random streams and ASM-style directed tests that execute across simulation, emulation, FPGA prototypes, and silicon. [C1]

This portability supports a shift-left methodology: tests created during RTL bring-up can remain useful in later validation stages and even in silicon. [C2]

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RELATIONSHIPS

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STING ← implements 97% 3e

STING generates portable stimulus that runs across simulation, emulation, prototyping, and silicon.

LINKED ENTITIES

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STING generates Evidence states that STING generates portable, self-checking RISC-V programs and supports constrained-random and directed stimulus.

ImperasDV debug_complement Evidence states that portable, self-checking tests can be combined with lock-step compare in ImperasDV to identify mismatches and simplify root-cause analysis.

VCS simulation_environment Evidence states that VCS executes STING-generated random tests and supports deterministic replay of failing cases.

Verdi coverage_debug_integration Evidence states that Verdi is used for waveforms, mismatch tracking, and functional coverage reporting, and that ImperasFC/SC results can be merged into Verdi.

CITATIONS

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12 citations — click to expand

[1] Portable stimulus is illustrated by STING-generated C++ random streams and ASM-style directed tests that execute across simulation, emulation, prototyping, and silicon. source

[2] Portability enables shift-left verification because tests developed during RTL bring-up remain useful in later validation stages and silicon. source

[3] RISC-V verification complexity is increased by the ISA's modular design and optional extensions, and comprehensive coverage requires multiple stimulus techniques. source

[4] A hybrid strategy combines constrained-random stimulus for breadth with directed suites for precise closure; random testing can miss features such as privilege transitions, page-table walks, and memory protection. source

[5] STING is a bare-metal RISC-V verification tool that generates constrained-random and directed tests and produces portable, self-checking programs. source

[6] STING-generated programs are architecturally self-checking and portable across simulation, ZeBu emulation, HAPS FPGA prototypes, and silicon. source

[7] ZeBu emulation is used for hardware-assisted verification of long software-driven tests, OS bring-up, and large-scale workloads. source

[8] HAPS prototyping is an FPGA-based prototyping solution for pre-silicon software development, performance validation, and extended regression cycles. source

[9] Architecturally self-checking tests combined with lock-step compare in ImperasDV help identify mismatches immediately and simplify root-cause analysis. source

[10] The methodology scales from simple embedded cores to complex multi-hart systems, while logged seeds and directed reruns support reproducible regression cycles. source

[11] Constrained-random stimulus from STING uncovers unexpected behavior, while ImperasTS directed suites provide structured compliance and feature coverage; together they accelerate coverage closure and reduce late bug escapes. source

[12] Coverage and debug integration can merge ImperasFC/SC results into Verdi and replay failing cases deterministically in VCS. source