Overview
Portable Stimulus is a verification concept in which generated tests remain usable across multiple execution targets. In the RISC-V verification flow described in the evidence, portable stimulus is illustrated by STING-generated C++ random streams and ASM-style directed tests that execute across simulation, emulation, FPGA prototypes, and silicon. [C1]
This portability supports a shift-left methodology: tests created during RTL bring-up can remain useful in later validation stages and even in silicon. [C2]
Role in RISC-V verification
RISC-V processor verification is challenging because the ISA is modular and includes many optional extensions. The cited flow argues that comprehensive coverage requires more than one verification or comparison methodology and more than one stimulus technique. [C3]
Portable stimulus is used as part of a hybrid strategy that combines constrained-random stimulus for broad exploration with directed suites for precise closure. Random testing can uncover unexpected behavior, while directed tests systematically target features such as privilege-mode transitions, page-table walks, and memory protection. [C4]
STING as an example generator
The evidence identifies STING as a bare-metal functional verification tool for RISC-V. It generates constrained-random and directed tests and produces portable, self-checking programs that can run across simulation, emulation, FPGA prototypes, and silicon. [C5]
STING-generated programs are described as architecturally self-checking. They are portable across simulation, ZeBu emulation, HAPS FPGA prototypes, and silicon, which makes them reusable across different validation stages. [C6]
Execution platforms
The cited flow explicitly connects portable stimulus to the following execution targets:
- Simulation, including RTL simulation environments. [C1]
- ZeBu emulation, used for hardware-assisted verification of long software-driven tests, OS bring-up, and large-scale workloads. [C7]
- HAPS FPGA prototyping, used for pre-silicon software development, performance validation, and extended regression cycles. [C8]
- Silicon, enabling tests developed earlier to continue providing value after fabrication. [C2]
Verification benefits
The evidence attributes several benefits to portable stimulus in the RISC-V verification lifecycle:
- Reuse across stages: Tests developed during RTL bring-up remain valuable through later validation and silicon. [C2]
- Shift-left enablement: Portable tests allow validation activity to begin earlier and carry forward into emulation, prototyping, and silicon. [C2]
- Debug support: Portable, self-checking tests can be combined with lock-step comparison in ImperasDV to identify mismatches immediately and simplify root-cause analysis. [C9]
- Scalability and reproducibility: The cited methodology scales from simple embedded cores to complex multi-hart systems, with logged seeds and directed reruns supporting reproducible regressions. [C10]
Relationship to coverage closure
Portable stimulus contributes to coverage closure when used with both random and directed test generation. The cited flow states that constrained-random stimulus from STING uncovers unexpected behavior, while directed suites such as ImperasTS provide structured compliance and feature coverage. Together, they accelerate coverage closure and reduce late bug escapes. [C11]
The flow also describes integration with coverage and debug infrastructure: ImperasFC/SC results can be merged into Verdi, and failing cases can be replayed deterministically in VCS. [C12]