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ISA semantics for ARMv8-a, RISC-V, and CHERI-MIPS

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First seen 9/5/2026

Last seen 9/5/2026

Evidence 2 chunks

01

NEIGHBORHOOD

5 nodes · 8 edges

graph · ISA semantics for ARMv8-a, RISC-V, and CHERI-MIPS · depth=1

02

RELATIONSHIPS

4 connections

Registered Report: Generating Test Suites for GPU Instruction Sets through Mutation and Equivalence Checking ← mentions 90% 1e evidence

The paper cites the ISA semantics paper for ARMv8-a, RISC-V, and CHERI-MIPS as related work.

Sail uses → 85% 1e evidence

The ISA semantics paper uses the SAIL language for specifying instruction set semantics.

ARMv8 instruction set mentions → 95% 1e evidence

The paper covers ARMv8-a ISA semantics.

RISC-V mentions → 95% 1e evidence

The paper covers RISC-V ISA semantics.