ARMv8 instruction set

Concept

The ARMv8 instruction set is a reduced instruction set computer (RISC) architecture developed by ARM, for which formal executable semantics have been published. It is referenced in research on mutation-based test generation for GPU instruction sets and is one of the ISAs covered by an integrated ISA semantics paper covering ARMv8-A, RISC-V, and CHERI-MIPS.

First seen 9/5/2026

Last seen 9/5/2026

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Overview

The ARMv8 instruction set is the instruction set architecture (ISA) introduced by ARM as the first 64-bit extension of the ARM architecture. It has been the subject of formal executable ISA semantics research, and is mentioned in academic work that develops mutation-based test suite generation methods for instruction set simulators.

Formal semantics

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RELATIONSHIPS

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Registered Report: Generating Test Suites for GPU Instruction Sets through Mutation and Equivalence Checking ← mentions 80% 1e

The paper mentions ARMv8 in the context of related ISA semantics work.

ISA semantics for ARMv8-a, RISC-V, and CHERI-MIPS ← mentions 95% 1e

The paper covers ARMv8-a ISA semantics.

LINKED ENTITIES

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Registered Report: Generating Test Suites for GPU Instruction Sets through Mutation and Equivalence Checking MENTIONS Extracted graph relationship

ISA semantics for ARMv8-a, RISC-V, and CHERI-MIPS MENTIONS Extracted graph relationship

CITATIONS

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3 citations — click to collapse

[1] A formal executable semantics for ARMv8-A was published by Armstrong et al. in POPL 2019, jointly with RISC-V and CHERI-MIPS (DOI 10.1145/3290384). Registered Report: Generating Test Suites for GPU Instruction Sets through Mutation and Equivalence Checking

[2] The Shitrit et al. registered report mutates a stand-alone ISA semantics and uses equivalence checking to surface inputs that trigger injected bugs, in contrast to prior work that instruments the executable specification of the ISA inside an instruction set simulator to obtain path coverage and uses CVC4 to solve path constraints. Registered Report: Generating Test Suites for GPU Instruction Sets through Mutation and Equivalence Checking

[3] A complete formal semantics of x86-64 user-level ISA was published by Dasgupta, Park, Kasampalis, Adve, and Rosu at PLDI 2019 (DOI 10.1145/3314221.3314601), cited alongside ARMv8 ISA-semantics work in mutation-based testing research. Registered Report: Generating Test Suites for GPU Instruction Sets through Mutation and Equivalence Checking