Registered Report: Generating Test Suites for GPU Instruction Sets through Mutation and Equivalence Checking
PaperFirst seen 9/5/2026
Last seen 9/5/2026
Evidence 16 chunks
NEIGHBORHOOD
46 nodes · 69 edgesgraph · Registered Report: Generating Test Suites for GPU Instruction Sets through Mutation and Equivalence Checking · depth=1
RELATIONSHIPS
47 connectionsThe paper uses CBMC as its bounded model checker for equivalence checking of C programs.
The paper introduces a pipeline for automatic test suite generation using mutation and equivalence checking.
The paper uses mutation testing to introduce bugs in the formal semantics.
The paper uses counterexamples from CBMC to build the test suite.
The paper uses equivalence checking to compare mutated and original semantics to generate counterexamples.
The paper uses MUSIC as its mutation testing engine to generate mutants.
The paper uses stratified random sampling as a comparison baseline for test suite generation.
The paper evaluates the pipeline on a formal semantics of NVIDIA's PTX instruction set.
The paper evaluates libFuzzer as a comparison to equivalence checking.
The paper uses bounded model checking to check equivalence between original and mutated semantics.
The paper constructs test suites from executable semantics expressed as C programs.
The paper finds that mutation generation can introduce undefined behaviour in C programs.
The paper discusses non-determinism introduced by mutations that makes testing nearly impossible without specialized instrumentation.
The paper discusses subnormal floating point numbers as critical test inputs to expose bugs.
The paper focuses on using ISA formal semantics as the basis for test generation.
The paper mentions x86 instruction set in the context of related work on formal semantics and model checkers.
The paper is focused on test suite generation for GPU instruction sets.
The paper evaluates CBMC as the equivalence checker in their pipeline, measuring its effectiveness and cost.
The paper demonstrates its technique using the add.rm.ftz.sat.f32 C semantics as a running example.
The paper mentions CVC3 as a solver used in differential symbolic execution related work.
The paper targets GPU instruction set testing as its primary application domain.
The paper cites the ISA semantics paper for ARMv8-a, RISC-V, and CHERI-MIPS as related work.
The paper uses formal semantics of instruction sets as the foundation for its test generation approach.
The paper measures mutation score to evaluate test suite effectiveness.
The paper relies on CBMC's support for IEEE floating point semantics to generate tests for floating point instructions.
CBMC converts C programs into SMT-LIB logical models for assertion checking.
CBMC uses SAT/SMT solvers to discharge assertions about C programs.
The paper cites the complete formal semantics of x86-64 paper as related work.
The paper compares the equivalence checker (CBMC) against libFuzzer for generating mutation-detecting inputs.
The paper mentions RISC-V in the context of related ISA semantics work.
The paper mentions litmus tests as an orthogonal strategy for testing instructions that enforce memory consistency.
The paper mentions differential testing in relation to a related work that randomizes testing on real hardware.
The paper discusses coverage-guided fuzzing as a related technique for generating test inputs for instruction set simulators.
The paper mentions dynamic symbolic execution as a related technique used to trigger mutation-detecting assertions.
The paper's approach is essentially model-based test generation with the formal semantics as the model.
The paper discusses path coverage in the context of related work that instruments ISA simulators.
The paper mentions differential symbolic execution as a related technique for finding inputs that detect differences between programs.
Sreepathi Pai is listed as an author of this paper.
Shoham Shitrit is listed as an author of this paper.
The paper mentions that C programs can be extracted from formal semantics encoded in SAIL.
The paper mentions the K framework as an alternative source for executable models.
The paper mentions ARMv8 in the context of related ISA semantics work.
The paper mentions KLEE as an alternative symbolic execution tool for equivalence checking.
The paper mentions SeaHorn as an alternative equivalence checker.
The paper mentions LLBMC but notes it does not support floating-point instructions.
The paper uses CBMC with the built-in MiniSAT solver for equivalence checks.
The paper mentions CVC4 as a solver used in related work for path constraints.