Model-based Test Generation
ConceptModel-based test generation is a simulation-based processor-verification approach in which test generators use an input-format specification to guide the generation of processor-level stimuli. In the cited processor-verification literature, it is discussed alongside constraint-based, coverage-guided, machine-learning, symbolic-execution, and fuzzing-based techniques.
First seen 5/26/2026
Last seen 6/8/2026
Evidence 7 chunks
Wiki v1
WIKI
Overview
Model-based test generation is described in the processor-verification literature as a direction within simulation-based test generation. In this approach, model-based test generators use an input format specification to guide the generation process for processor-level verification stimuli.
Use in processor verification
NEIGHBORHOOD
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3 connectionsCoverage-guided fuzzing is contrasted with traditional generational/model-based test generation approaches.
The paper mentions model-based test generators as related work.
Bayesian network coverage-directed test generation is an alternative approach to model-based test generation.
LINKED ENTITIES
7 linksProcessor Verification application_domain The evidence states that simulation-based approaches relying on test generation have a long history in the processor verification domain and discusses model-based test generators in that context.
Constraint Satisfaction Problem related_technique The evidence states that constraints are leveraged for specification purposes and processed by CSP solvers.
Satisfiability Modulo Theories related_technique The evidence states that constraints are leveraged for specification purposes and processed by SMT solvers.
coverage-guided test generation related_technique The evidence lists coverage-guided test generation based on Bayesian networks as another notable approach.
Symbolic Execution related_technique The evidence states that symbolic execution techniques have been used for test-case generation at the ISS level.
Coverage-guided Fuzzing related_technique The evidence discusses coverage-guided fuzzing approaches in the same processor-verification and RISC-V verification context.
RISC-V verification_context The evidence discusses RISC-V verification techniques in relation to test generation, constraint-based specifications, and fuzzing.
CITATIONS
8 sources8 citations — click to expand
[1] Model-based test generators use an input format specification to guide the generation process. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[2] Simulation-based approaches relying on test generation have a long history in processor verification and aim to improve processor-level stimulus generation. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[3] Constraints can be used for specification and processed by CSP or SMT solvers in related processor test-generation approaches. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[4] Optimization techniques have been proposed to propagate constraints among multiple instructions more effectively. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[5] Processor manuals have been mined to obtain input models automatically for test-generation purposes. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[6] Related approaches include coverage-guided test generation based on Bayesian networks and other machine-learning techniques. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[7] Symbolic execution techniques have been used for test-case generation at the ISS level. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[8] For RISC-V, related verification techniques include semi hand-written directed test suites, randomized-pattern generation, constraint-based specifications, and coverage-guided fuzzing. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing