Satisfiability Modulo Theories

Concept

Satisfiability Modulo Theories (SMT) is a solving approach used in formal verification and other constraint-encoding tasks. The provided evidence describes SMT-LIB and SMT-LIB2 as standard solver-facing languages for expressing SMT problems, including bit-vector constraints, functions, assertions, and satisfiability checks. SMT solvers such as z3 and cvc5 are used in Verilator’s constrained-randomization flow, where SystemVerilog constraints are converted to SMT-LIB2 and solved to obtain satisfying assignments.

First seen 5/25/2026

Last seen 7/8/2026

Evidence 7 chunks

Wiki v2

WIKI

Overview

Satisfiability Modulo Theories (SMT) is described in the provided sources as a core tool in formal verification. The SMT-LIB specification language can be used to interact with theorem-proving or SMT-solving software, while higher-level interfaces may make complex SMT formulae easier to specify. [C1]

In the SMT-LIB2 representation described by Antmicro, an SMT problem is expressed in a Lisp-like language in terms of functions and constraints, called assertions in SMT terminology. Variables are represented as 0-argument functions. [C2]

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RELATIONSHIPS

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EPEX ← uses 100% 2e

EPEX makes use of an SMT solver for formal reasoning.

Verilator ← uses 1e

Verilator uses SMT solvers in the implementation of randomization constraints.

Z3 ← implements 1e

z3 is an SMT solver implementing Satisfiability Modulo Theories.

cvc5 ← implements 1e

cvc5 is an SMT solver implementing Satisfiability Modulo Theories.

SMT-LIB2 uses → 1e

SMT-LIB2 is the standard language used to describe Satisfiability Modulo Theories problems.

LINKED ENTITIES

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Verilator USES Extracted graph relationship

Z3 IMPLEMENTS Extracted graph relationship

cvc5 IMPLEMENTS Extracted graph relationship

SMT-LIB2 USES Extracted graph relationship

CITATIONS

10 sources

10 citations — click to expand

[1] SMT is a core tool in formal verification, and SMT-LIB can be used to interact with theorem-proving software. Satisfiability.jl: Satisfiability Modulo Theories in Julia

[2] SMT-LIB2 describes SMT problems using functions and constraints/assertions, with variables represented as 0-argument functions. Constrained randomization in Verilator: SystemVerilog constraint to SMT-LIB2 conversion

[3] An SMT-LIB2-compliant solver can report satisfiability and provide concrete model values for a satisfiable problem. Constrained randomization in Verilator: SystemVerilog constraint to SMT-LIB2 conversion

[4] SMT-LIB2 bit-vector signedness is determined by the operation, such as bvslt for signed less-than and bvult for unsigned less-than. Constrained randomization in Verilator: SystemVerilog constraint to SMT-LIB2 conversion

[5] z3 and cvc5 are identified as SMT solvers in the Verilator constrained-randomization context. Constrained randomization in Verilator: SystemVerilog constraint to SMT-LIB2 conversion

[6] SMT solvers are typically deterministic, so Verilator’s constrained-randomization work adds an artificial random-hash constraint to encourage different solutions. Constrained randomization in Verilator: SystemVerilog constraint to SMT-LIB2 conversion

[7] Verilator converts SystemVerilog expressions to SMT-LIB2 strings for constrained randomization, including converting logical expressions into solver-digestible SMT-LIB2 forms. Constrained randomization in Verilator: SystemVerilog constraint to SMT-LIB2 conversion

[8] Verilator converts each constraint to a separate function; future or ongoing work includes state-dependent constraints, conditional constraints, arrays, and better handling of SMT-LIB2’s boolean versus 1-bit-vector distinction. Constrained randomization in Verilator: SystemVerilog constraint to SMT-LIB2 conversion

[9] EPEX uses a formal ISA model and SMT reasoning to generate equivalent test programs for processor verification, checking that original and equivalent programs preserve equal architectural states and reporting bug-finding on VexRiscv. EPEX: Processor Verification by Equivalent Program Execution

[10] Grammatical inference has been formulated as an SMT problem with encodings for deterministic finite automata and extensions for Moore and Mealy machines. Grammatical Inference as a Satisfiability Modulo Theories Problem