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EPEX

Tool ☆ WATCH ⎘ SHARE

First seen 6/22/2026

Last seen 6/22/2026

Evidence 14 chunks

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NEIGHBORHOOD

1 nodes · 0 edges

graph · EPEX · depth=1

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RELATIONSHIPS

26 connections

epex-formal-rv32-model uses → 100% 2e evidence

EPEX uses the epex-formal-rv32-model as its formal ISA model for generating equivalent programs.

Equivalent Program Execution implements → 100% 2e evidence

EPEX implements the Equivalent Program Execution technique for processor verification.

Equivalence Checking implements → 100% 2e evidence

EPEX is based on a new form of equivalence checking.

Formal ISA Model uses → 100% 2e evidence

EPEX uses a formal ISA model to generate equivalent instruction sequences.

Satisfiability Modulo Theories uses → 100% 2e evidence

EPEX makes use of an SMT solver for formal reasoning.

VexRiscv evaluates → 100% 2e evidence

EPEX is evaluated on the VexRiscv processor to demonstrate bug-finding capabilities.

Processor Verification implements → 100% 2e evidence

EPEX implements a novel approach to processor verification.

test program generation implements → 100% 2e evidence

EPEX automatically broadens and generates equivalent test programs.

ISA-level Verification implements → 95% 2e evidence

EPEX performs verification at the ISA level.

Control Path Variation uses → 90% 2e evidence

EPEX measures and exploits control path variation to improve verification coverage.

Instruction Sequence Equivalence implements → 100% 2e evidence

EPEX implements instruction sequence equivalence as the core concept for generating equivalent programs.

RISC-V ISA uses → 100% 2e evidence

EPEX targets and uses the RISC-V ISA for its formal model and test generation.

Architectural State uses → 100% 2e evidence

EPEX compares architectural states of two processor instances executing equivalent programs.

riscv-formal compares with → 85% 2e evidence

EPEX is compared with riscv-formal as both target RISC-V processor verification.

EPEX: Processor Verification by Equivalent Program Execution ← introduces 100% 2e evidence

The paper introduces the EPEX tool for processor verification by equivalent program execution.

Instruction Replacement implements → 100% 2e evidence

EPEX implements instruction replacement as a core mechanism for generating equivalent programs.

Z3 SMT solver uses → 100% 1e evidence

EPEX uses the Z3 SMT solver for efficient reasoning.

CBMC uses → 100% 1e evidence

EPEX uses CBMC to transform the C-based formal ISA model into SMT-lib format.

SMT-lib v2.0 uses → 100% 1e evidence

EPEX uses SMT-lib v2.0 as the intermediate format for formal reasoning.

Instruction Set Simulator uses → 100% 1e evidence

EPEX derives an ISS from the formal ISA model and uses it during verification.

Effect Constraint uses → 100% 1e evidence

EPEX uses the effect constraint to reduce de-facto NOPs during instruction replacement.

Chain Constraint uses → 100% 1e evidence

EPEX uses the chain constraint to generate linked instruction sequences.

simulation-based verification uses → 95% 1e evidence

EPEX can be used in a simulation-based verification environment.

mutation testing ← compares with 85% 1e evidence

EPEX mutation experiments compare its bug-finding ability against mutations not caught by other testing methods.

epex-formal-rv32-model introduces → 100% 1e evidence

EPEX introduces the formal RV32 ISA model as a code artifact.

Program Synthesis uses → 90% 1e evidence

Finding equivalent instruction sequences is a special case of program synthesis used in EPEX.