VexRiscv

Tool

VexRiscv is described by its GitHub repository as an FPGA-friendly 32-bit RISC-V CPU implementation. In the GLSVLSI 2022 paper “Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing,” it was used in a fuzzing-based processor-verification case study configured for RV32IM, where the authors reported decoder and CSR-related bugs.

First seen 5/25/2026

Last seen 7/12/2026

Evidence 29 chunks

Wiki v2

WIKI

Overview

VexRiscv is a 32-bit RISC-V CPU implementation hosted at the GitHub repository SpinalHDL/VexRiscv; the repository describes it as “A FPGA friendly 32 bit RISC-V CPU implementation.” [C1]

Verification case study

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NEIGHBORHOOD

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RELATIONSHIPS

13 connections

RISC-V implements → 100% 4e

VexRiscv implements the RISC-V RV32I ISA.

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing ← evaluates 100% 4e

The paper evaluates the VexRiscv RISC-V processor as the device under test.

SpinalHDL uses → 100% 3e

VexRiscv is built using SpinalHDL as its hardware description language.

pipelining implements → 100% 3e

VexRiscv is a 4-stage pipelined RTL-core.

Cascade ← evaluates 100% 2e

Cascade is evaluated on VexRiscv and finds bugs in it

RV32IM implements → 100% 2e

VexRiscv is configured to support the RV32IM instruction set in the case study.

RV32IM evaluates → 100% 2e

VexRiscv is configured to support the RV32IM instruction subset in the case study.

RISC-V ISA implements → 100% 2e

VexRiscv is a RISC-V processor implementation.

Processor Verification using Symbolic Execution: A RISC-V Case-Study ← mentions 85% 2e

The paper mentions VexRiscV as a popular SpinalHDL-based processor.

EPEX ← evaluates 100% 2e

EPEX is evaluated on the VexRiscv processor to demonstrate bug-finding capabilities.

SpinalHDL part of → 90% 1e

VexRiscV is a popular open source processor implementation based on SpinalHDL.

A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors ← mentions 90% 1e

The paper mentions VexRiscv in the table of selected RISC-V cores.

SpinalHDL derived from → 90% 1e

VexRiscV is based on SpinalHDL hardware description language.

LINKED ENTITIES

5 links

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing EVALUATES Extracted graph relationship

RISC-V IMPLEMENTS Extracted graph relationship

pipelining IMPLEMENTS Extracted graph relationship

RV32IM IMPLEMENTS Extracted graph relationship

SpinalHDL USES Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] VexRiscv is described as an FPGA-friendly 32-bit RISC-V CPU implementation hosted at SpinalHDL/VexRiscv. SpinalHDL/VexRiscv

[2] The GLSVLSI 2022 paper cites the VexRiscv repository and a specific VexRiscv commit. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[3] In the paper’s evaluation, VexRiscv was configured to support RV32IM, and the authors found decoder and CSR-related errors. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[4] The paper reports decoder bugs involving execution of RV64I LWU on the RV32IM configuration and illegal-instruction decoding issues in SLLI, SRLI, and SRAI. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[5] The paper reports CSR bugs involving missing write exceptions for read-only ID and counter CSRs, and erroneous read exceptions for several counter-related CSRs. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing