SpinalHDL

Tool

SpinalHDL is referenced in the supplied evidence as part of hardware RTL and verification workflows: a RISC-V verification study obtained a Verilog RTL implementation from SpinalHDL and processed it with Verilator, while later fuzzing work cites SpinalFuzz as a coverage-guided fuzzer for SpinalHDL designs and references the VexRiscv repository under the SpinalHDL GitHub organization.

First seen 5/26/2026

Last seen 5/30/2026

Evidence 5 chunks

Wiki v1

WIKI

Overview

SpinalHDL appears in the supplied verification literature as a tool or design ecosystem used around hardware RTL generation and testing. In one RISC-V cross-level processor-verification evaluation, the authors report that they obtained a Verilog RTL implementation from SpinalHDL, then used Verilator to translate that RTL into a C++ description for a SystemC-based co-simulation testbench. The same evaluation describes the tested RTL core as configurable at the microarchitectural level, with examples including shifter implementation and pipeline levels, and states that the experiments used the standard configuration available to customers.

Use in processor verification

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NEIGHBORHOOD

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RELATIONSHIPS

3 connections

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← uses 100% 2e

The paper uses SpinalHDL to obtain the Verilog RTL implementation of the TGF core.

VexRiscv ← uses 100% 2e

VexRiscv is written in SpinalHDL.

SpinalFuzz ← uses 90% 2e

SpinalFuzz is a fuzzer targeting SpinalHDL designs.

LINKED ENTITIES

2 links

Verilator used_with The evidence states that after obtaining the Verilog RTL implementation from SpinalHDL, the authors applied Verilator to obtain a C++ description of the core.

SpinalFuzz targets_designs_from The evidence cites 'SpinalFuzz: Coverage-Guided Fuzzing for SpinalHDL Designs' and describes a fuzzer for SpinalHDL designs that automates input corpus and fuzzer harness generation.

CITATIONS

6 sources

6 citations — click to expand

[1] A RISC-V verification evaluation obtained a Verilog RTL implementation from SpinalHDL and used Verilator to obtain a C++ core description embedded in a SystemC-based co-simulation testbench.

[2] The evaluated RTL core was described as microarchitecturally configurable, with examples including shifter implementation and pipeline levels, and the evaluation used the standard customer-available configuration.

[3] The verification workflow used a 32-bit RISC-V ISS from the open-source RISC-V VP, modified to match the RTL core capabilities, and the RTL core supported RV32I with machine-mode CSRs.

[4] The RISC-V verification process iterated between testing and bug fixing; the unprivileged ISA implementation was described as mature, and most reported bugs concerned the privileged ISA, particularly CSR handling.

[5] SpinalFuzz is cited as 'Coverage-Guided Fuzzing for SpinalHDL Designs,' and the related-work discussion describes a fuzzer for SpinalHDL designs that automates generation of an input corpus and fuzzer harness. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[6] The coverage-guided fuzzing paper presents VexRiscv as a popular open-source RISC-V-based processor case study and lists its repository as https://github.com/SpinalHDL/VexRiscv with commit 98de02051e1a5c9400c022dc61acd4bd0507f8a5. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing