Skip to content
STIMSMITH

SpinalHDL

Tool WIKI v1 · 5/26/2026

SpinalHDL is referenced in the supplied evidence as part of hardware RTL and verification workflows: a RISC-V verification study obtained a Verilog RTL implementation from SpinalHDL and processed it with Verilator, while later fuzzing work cites SpinalFuzz as a coverage-guided fuzzer for SpinalHDL designs and references the VexRiscv repository under the SpinalHDL GitHub organization.

Overview

SpinalHDL appears in the supplied verification literature as a tool or design ecosystem used around hardware RTL generation and testing. In one RISC-V cross-level processor-verification evaluation, the authors report that they obtained a Verilog RTL implementation from SpinalHDL, then used Verilator to translate that RTL into a C++ description for a SystemC-based co-simulation testbench. The same evaluation describes the tested RTL core as configurable at the microarchitectural level, with examples including shifter implementation and pipeline levels, and states that the experiments used the standard configuration available to customers.

Use in processor verification

In the cited RISC-V verification workflow, the RTL implementation obtained from SpinalHDL was compared against an instruction-set simulator reference model. The authors used a 32-bit RISC-V ISS from the open-source RISC-V VP, modified it to match the RTL core capabilities, and state that the RTL core supported the RV32I ISA together with machine-mode CSRs. Their process iterated between testing and bug fixing until no more bugs were found; they report that the unprivileged ISA implementation was already mature and that most bugs were related to the privileged ISA, especially CSR handling.

Fuzzing and related tooling

A later paper on efficient cross-level processor verification using coverage-guided fuzzing cites SpinalFuzz as “Coverage-Guided Fuzzing for SpinalHDL Designs” and states that this fuzzer automates generation of an input corpus and fuzzer harness. The same paper also uses VexRiscv as a case study and describes it as a popular open-source RISC-V-based processor; its references list the project at https://github.com/SpinalHDL/VexRiscv with a specific commit identifier.

Evidence-limited notes

The supplied evidence supports SpinalHDL’s role in obtaining Verilog RTL for a RISC-V core verification flow and as the design target of SpinalFuzz. It does not provide a full language specification, release history, licensing details, or independent feature list for SpinalHDL itself.

LINKED ENTITIES

2 links
Verilator used_with
SpinalFuzz targets_designs_from

CITATIONS

6 sources
6 citations
[1] A RISC-V verification evaluation obtained a Verilog RTL implementation from SpinalHDL and used Verilator to obtain a C++ core description embedded in a SystemC-based co-simulation testbench.
[2] The evaluated RTL core was described as microarchitecturally configurable, with examples including shifter implementation and pipeline levels, and the evaluation used the standard customer-available configuration.
[3] The verification workflow used a 32-bit RISC-V ISS from the open-source RISC-V VP, modified to match the RTL core capabilities, and the RTL core supported RV32I with machine-mode CSRs.
[4] The RISC-V verification process iterated between testing and bug fixing; the unprivileged ISA implementation was described as mature, and most reported bugs concerned the privileged ISA, particularly CSR handling.
[5] SpinalFuzz is cited as 'Coverage-Guided Fuzzing for SpinalHDL Designs,' and the related-work discussion describes a fuzzer for SpinalHDL designs that automates generation of an input corpus and fuzzer harness. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[6] The coverage-guided fuzzing paper presents VexRiscv as a popular open-source RISC-V-based processor case study and lists its repository as https://github.com/SpinalHDL/VexRiscv with commit 98de02051e1a5c9400c022dc61acd4bd0507f8a5. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing