Overview

VexRiscv is a 32-bit RISC-V CPU implementation hosted at the GitHub repository SpinalHDL/VexRiscv; the repository describes it as “A FPGA friendly 32 bit RISC-V CPU implementation.” [C1]

Verification case study

The GLSVLSI 2022 paper “Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing” cites VexRiscv as a referenced design under the SpinalHDL/VexRiscv repository, including a specific commit hash in its bibliography. [C2]

In the paper’s evaluation, the authors configured VexRiscv to support the RV32IM instruction subset. Their manual analysis reports errors associated with instruction decoding and many errors associated with CSRs. [C3]

Reported decoder issues

For the RV32IM configuration used in the study, the authors report that VexRiscv executed the RV64I LWU instruction, even though that instruction is valid only on a 64-bit RISC-V core and should not execute on the configured 32-bit RV32IM core. They also report illegal-instruction handling issues traced to three similar decoding bugs in SLLI, SRLI, and SRAI, where encodings contained an incorrect additional “don’t care” bit, causing illegal instructions to be misinterpreted as those shift instructions. [C4]

Reported CSR issues

The same manual analysis reports CSR-related bugs. For the read-only ID CSRs mvendorid, marchid, mimpid, and mhartid, VexRiscv was reported not to raise an exception on write attempts. The authors also report the same write-exception issue for the read-only counter CSRs cycle, cycleh, instret, and instreth. Conversely, they report that VexRiscv raised exceptions on reads to several counter-related CSRs that should have allowed read access, including time, timeh, hpmcounter, hpmcounterh, mcounteren, mhpmcounter3-31, mhpmcounter3-31h, and mhpmevent. [C5]

Relationship to RISC-V and RV32IM

The provided sources support characterizing VexRiscv as a RISC-V CPU implementation and document a verification configuration targeting the RV32IM subset. [C1] [C3]