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RV32IM

Concept

RV32IM is a RISC-V instruction subset/configuration referenced in a coverage-guided fuzzing case study of the VexRiscv RTL core. In that evaluation, VexRiscv was configured to support RV32IM, which established a 32-bit instruction-set boundary: the RV64I-only LWU instruction should not execute, and several decoder and CSR conformance bugs were reported.

First seen 5/26/2026
Last seen 6/8/2026
Evidence 6 chunks
Wiki v2

WIKI

Overview

RV32IM is described in the available evidence as a RISC-V instruction subset used as the configured target for a VexRiscv processor-verification evaluation. The RISC-V ISA includes 32-bit, 64-bit, and 128-bit base integer sets such as RV32I, RV64I, and RV128I, and optional standard extensions such as multiply/divide (M) and compressed instructions (C). In the cited case study, VexRiscv was configured to support the RV32IM instruction subset. [citation: RISC-V ISA structure and RV32IM configuration]

Role in the VexRiscv fuzzing case study

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NEIGHBORHOOD

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RELATIONSHIPS

6 connections
VexRiscv ← evaluates 100% 2e
VexRiscv is configured to support the RV32IM instruction subset in the case study.
Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing ← uses 100% 2e
The paper uses the RV32IM configuration of VexRiscv in its case study.
VexRiscv ← implements 100% 2e
VexRiscv is configured to support the RV32IM instruction set in the case study.
RISC-V part of → 100% 1e
RV32IM is a RISC-V configuration combining the RV32I base with the multiply/divide extension.
Synthesizing Instruction Selection Rewrite Rules from RTL using SMT ← evaluates 100% 1e
The paper evaluates rewrite rule synthesis for the RV32IM ISA.
RV32I extends → 100% 1e
RV32IM extends RV32I with multiplication, division, and remainder instructions.

LINKED ENTITIES

2 links
Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing USES Extracted graph relationship
VexRiscv IMPLEMENTS Extracted graph relationship

CITATIONS

8 sources
8 citations — click to expand
[1] RISC-V ISA structure and RV32IM configuration Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[2] Co-simulation fuzzing workflow Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[3] VexRiscv RV32IM evaluation Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[4] LWU outside RV32IM boundary Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[5] RV32IM decoder bugs Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[6] ID CSR write-exception bugs Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[7] Counter CSR bugs Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[8] RV32IM verification significance Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing