RV32I

Concept

RV32I is treated in the cited RISC-V verification evidence as a 32-bit RISC-V ISA configuration. In one cross-level testing case study, an RTL core supported the RV32I ISA together with machine-mode CSRs; later fuzzing work configured VexRiscv for RV32IM and identified decoder errors involving RV64I-only and illegal instruction encodings.

First seen 5/26/2026

Last seen 6/8/2026

Evidence 14 chunks

Wiki v2

WIKI

Overview

RV32I is referenced in the cited verification literature as a 32-bit RISC-V ISA configuration. In a cross-level testing case study, the RTL core under test supported the RV32I ISA in combination with machine-mode CSRs. The study used a 32-bit RISC-V instruction-set simulator from the open-source RISC-V VP as the ISS reference model and modified it to exactly match the RTL core's supported instruction set and CSRs.

Verification context

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NEIGHBORHOOD

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RELATIONSHIPS

9 connections

RISC-V part of → 100% 5e

RV32I is the base integer instruction set of RISC-V.

Synthesizing Instruction Selection Rewrite Rules from RTL using SMT ← evaluates 100% 2e

The paper evaluates rewrite rule synthesis for the RV32I base RISC-V ISA.

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← uses 100% 2e

The paper targets the RV32I ISA configuration in its case study.

Instruction Set Architecture (ISA) part of → 95% 1e

RV32I defines integer calculations, program control, load/store and debugging instructions.

insns/generate.py ← introduces 88% 1e

insns/generate.py can generate additional ISA combinations including rv32i variants

RV32IM ← extends 100% 1e

RV32IM extends RV32I with multiplication, division, and remainder instructions.

RV32IF ← extends 100% 1e

RV32IF extends RV32I with floating-point support.

RISC-V ISA part of → 100% 1e

RV32I is the base integer instruction set of the RISC-V ISA.

MINRES The Good Folk (TGF) Series RTL core ← implements 100% 1e

The MINRES TGF RTL core implements the RV32I ISA with machine mode CSRs.

LINKED ENTITIES

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Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study USES Extracted graph relationship

CITATIONS

7 sources

7 citations — click to expand

[1] An RTL core in the cross-level testing case study supported the RV32I ISA in combination with machine-mode CSRs. Efficient Cross-Level Testing for

[2] The cross-level testing setup used a 32-bit RISC-V ISS from the open-source RISC-V VP and modified it to match the RTL core's supported instruction set and CSRs. Efficient Cross-Level Testing for

[3] The 2020 testing process found the unprivileged RISC-V ISA implementation mature, with most bugs related to privileged-ISA CSR handling and 10 bugs found in total. Efficient Cross-Level Testing for

[4] The instruction generator used sequences such as two-instruction large-immediate loads, compute chains using operations such as ADD and SUB, and CSR-access sequences. Efficient Cross-Level Testing for

[5] In the 2022 fuzzing evaluation, VexRiscv was configured for RV32IM, but a decoder bug caused it to execute the RV64I LWU instruction, which the paper states is valid only on a 64-bit and not a 32-bit RISC-V core. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[6] The 2022 fuzzing evaluation found illegal-instruction decoding bugs involving SLLI, SRLI, and SRAI due to incorrect don't-care bits in the encodings. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[7] The 2022 fuzzing evaluation reported CSR bugs involving read-only ID CSRs and counter-related CSRs. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing