Overview

Model-based test generation is described in the processor-verification literature as a direction within simulation-based test generation. In this approach, model-based test generators use an input format specification to guide the generation process for processor-level verification stimuli.

Use in processor verification

Simulation-based approaches that rely on test generation have a long history in the processor-verification domain. Within that area, model-based test generation is one method proposed to improve the generation of processor-level stimuli for verification purposes.

Specification and constraint handling

The cited evidence identifies input-format specifications as the guiding artifact for model-based test generators. It also notes related specification techniques in which constraints are used for specification and are processed by Constraint Satisfaction Problem (CSP) and Satisfiability Modulo Theories (SMT) solvers. Additional work has focused on propagating constraints among multiple instructions more effectively.

Automatically derived input models

One related approach mines processor manuals to obtain an input model automatically, which can then be used for test-generation purposes.

Related techniques

The same processor-verification context also includes coverage-guided test generation based on Bayesian networks, other machine-learning techniques, symbolic-execution-based test-case generation at the instruction-set-simulator level, and fuzzing-based techniques. For RISC-V verification specifically, the cited paper situates these approaches among semi hand-written directed test suites, randomized-pattern generation, constraint-based specifications, and coverage-guided fuzzing approaches.