Counterexample Generation — STIMSMITH

Counterexample Generation

Concept

Counterexample generation is the process, illustrated in UCLID5-based formal verification, of turning a satisfiable negated verification condition into a concrete sequence of model actions that violates the intended property. Such counterexamples help diagnose design errors, modeling inaccuracies or over-abstraction, and incorrectly stated verification conditions.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 1 chunks

Wiki v1

WIKI

Definition

Counterexample generation occurs when a formal verification workflow checks a verification condition by asking an SMT solver to satisfy the negation of the desired property, and the solver returns that the formula is satisfiable. In the UCLID5 workflow described in the evidence, the solver supplies concrete values for all data elements in the formula, including uninterpreted functions, and UCLID5 uses those values to construct a counterexample: a sequence of actions that could occur in the model and violate a verification condition. [counterexample-generation-from-satisfiability]

Role in a UCLID5 verification flow

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RELATIONSHIPS

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UCLID5 ← introduces 100% 1e

When a verification condition fails, UCLID5 generates a counterexample showing a sequence of actions that violate the condition.

LINKED ENTITIES

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UCLID5 generates_counterexamples The evidence states that UCLID5 uses concrete values returned by the SMT solver to generate a counterexample.

Z3 example_smt_solver_used_with_uclid5 The evidence states that the work used the Z3 solver developed at Microsoft Research as the SMT solver invoked by UCLID5.

CITATIONS

6 sources

6 citations — click to expand

[1] verification-condition-generation Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[2] counterexample-generation-from-satisfiability Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[3] solver-outcomes Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[4] counterexample-diagnostics Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[5] model-abstraction Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[6] uclid5-z3-context Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5