UCLID5

Tool

UCLID5 is a formal verification tool developed at Carnegie Mellon University and the University of California, Berkeley. It provides a modeling language and a command language for describing systems and verification scripts, supports hardware and software modeling, and generates verification conditions that can be checked by SMT solvers such as Z3.

First seen 5/25/2026

Last seen 5/26/2026

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Overview

UCLID5 is a formal verification tool described as the most recent in a series of tools developed at Carnegie Mellon University and the University of California, Berkeley. It provides both a modeling language for describing a system to be verified and a command language for creating verification scripts that specify initialization, operation, and verification conditions.

In a documented microprocessor-verification case study, UCLID5 was used to formally verify variants of the Y86-64 pipelined microprocessor against a sequential reference implementation. The study reports that UCLID5 was used to evaluate modeling and verification capabilities for hardware designs and that the verified pipeline processors generated the same results as the sequential reference model for all possible programs.

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RELATIONSHIPS

17 connections

Bit-Vector Modeling uses → 100% 2e

UCLID5 supports bit-vector types for precise hardware modeling.

Z3 SMT solver uses → 100% 2e

UCLID5 invokes the Z3 SMT solver to check satisfiability of verification conditions.

Uninterpreted Functions uses → 100% 2e

UCLID5 supports uninterpreted functions for term-level modeling of hardware blocks.

Term-Level Modeling uses → 100% 2e

UCLID5 supports term-level modeling as demonstrated by Burch and Dill for microprocessor verification.

State Machine Model uses → 100% 2e

UCLID5 models hardware as state machines computing next state from current state.

Pipelined Microprocessor evaluates → 100% 1e

UCLID5 is used to verify pipelined microprocessor designs by modeling and checking their correctness.

Semiconductor Research Corporation ← mentions 90% 1e

The Semiconductor Research Corporation provided funding support for the UCLID5 verification work.

National Science Foundation ← mentions 90% 1e

The National Science Foundation provided funding support for the UCLID5 verification work.

HCL2U Translator ← introduces 95% 1e

HCL2U automatically generates UCLID5 code from HCL descriptions of the processor control logic.

UCLID5 Pipeline Register Definition ← part of 100% 1e

The UCLID5 pipeline register definition is a code artifact used in the UCLID5 verification framework.

Pipeline Consistency Predicate ← part of 100% 1e

The pipeline consistency predicate is part of the UCLID5 model, restricting the initial pipeline state for verification.

Y86-64 evaluates → 100% 1e

UCLID5 is used to formally verify the Y86-64 pipelined microprocessor designs.

Memory Array Modeling uses → 90% 1e

UCLID5 supports memory array modeling as one option for modeling the data memory.

Burch-Dill Correspondence Checking implements → 100% 1e

UCLID5's verification script carries out Burch-Dill correspondence checking for pipelined microprocessors.

Satisfiability Modulo Theories (SMT) uses → 100% 1e

UCLID5 generates verification conditions expressed as SMT formulas and invokes an SMT solver.

Enumerated Types in Formal Modeling uses → 100% 1e

UCLID5 uses enumerated types to model fields with small numbers of possible values such as instruction codes.

Counterexample Generation introduces → 100% 1e

When a verification condition fails, UCLID5 generates a counterexample showing a sequence of actions that violate the condition.

LINKED ENTITIES

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Carnegie Mellon University DEVELOPED Extracted graph relationship

University of California, Berkeley DEVELOPED Extracted graph relationship

Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5 USES Extracted graph relationship

Z3 INVOKES Extracted graph relationship

Satisfiability Modulo Theories APPLIES Extracted graph relationship

Uninterpreted Functions APPLIES Extracted graph relationship

formal verification SUPPORTS Extracted graph relationship

CITATIONS

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9 citations — click to expand

[1] UCLID5 is a formal verification tool developed at Carnegie Mellon University and the University of California, Berkeley. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[2] UCLID5 provides both a modeling language and a command language for verification scripts. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[3] UCLID5 supports models combining synchronous hardware and software, with hardware modeled as state machines and software as sequences of state-updating operations. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[4] UCLID5 supports data types including uninterpreted types, integers, bit vectors, enumerated types, booleans, and arrays. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[5] UCLID5 can combine supported data types in functions and arrays, including uninterpreted functions used for abstract hardware behavior. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[6] UCLID5 generates verification conditions and invokes an SMT solver; the Y86-64 study used Z3. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[7] An SMT solver invoked by UCLID5 can return unsatisfiable, satisfiable with counterexample data, or indeterminate. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[8] The Y86-64 case study used UCLID5 to formally verify several variants of a pipelined microprocessor against a sequential reference model. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[9] The Y86-64 study reports that experimental results used UCLID5 version 0.9.5 and Z3 version 4.5.0. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5