Memory Array Modeling

Concept

Memory array modeling is a formal-verification modeling choice in which main memory is represented using an array data type. In the cited UCLID5 verification study for pipelined Y86-64 microprocessors, this precise array-based representation was compared with a more abstract alternative: treating memory state as an uninterpreted value and representing reads and writes with uninterpreted functions.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

Memory array modeling represents main memory using an array data type in a formal model. In the UCLID5 verification study of pipelined Y86-64 microprocessors, main memory could be modeled in either of two ways: as an array data type, or as an uninterpreted memory state with uninterpreted functions for read and write operations. [C1]

Modeling alternatives

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RELATIONSHIPS

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ALU Abstraction Modeling part of → 80% 1e

Memory array modeling is one choice in creating a formal model alongside ALU abstraction.

UCLID5 ← uses 90% 1e

UCLID5 supports memory array modeling as one option for modeling the data memory.

LINKED ENTITIES

2 links

UCLID5 used_in_verification_context The evidence is from a study titled "Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5" and discusses modeling choices in that verification context.

Uninterpreted Functions alternative_to_array_modeling The evidence states that memory could alternatively be treated as an uninterpreted value with uninterpreted functions representing read and write operations.

CITATIONS

4 sources

4 citations — click to collapse

[1] Main memory could be modeled either using an array data type or by treating memory state as an uninterpreted value with uninterpreted functions for read and write operations. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[2] The source describes abstraction levels as a partial ordering in which uninterpreted data types and uninterpreted functions are more abstract than concrete data types and precise mathematical functions. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[3] For the discussed pipelined implementations, memory operations are performed in program order, so the uninterpreted memory model sufficed. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[4] The study also tested the array-based memory model to explore performance implications of a more precise model. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5