HCL2U Translator

Tool

HCL2U is a translator used in a UCLID5-based verification framework for Y86-64 processor models. It converts Hardware Control Language (HCL) signal definitions into UCLID5 macro definitions, enabling control logic to be extracted directly from HCL descriptions and reused in formal verification models.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

The HCL2U Translator is a tool described in the verification framework for pipelined Y86-64 microprocessors using UCLID5. Its role is to translate control logic written in HCL (Hardware Control Language) into UCLID5 macro definitions. In the framework, HCL2U is one of the programs used to generate UCLID5 files for specific verification tasks, alongside a Python program that performs file merging and option selection.

Role in the verification workflow

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

2 connections

Hardware Control Language (HCL) uses → 100% 2e

The HCL2U translator takes HCL descriptions and generates UCLID5 code.

UCLID5 introduces → 95% 1e

HCL2U automatically generates UCLID5 code from HCL descriptions of the processor control logic.

CITATIONS

8 sources

8 citations — click to expand

[1] HCL2U translates HCL signal definitions into UCLID5 macro definitions. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[2] The UCLID5-generation workflow combines HCL control logic with functional-block frameworks, common data types, a system model, and a verification script; HCL2U handles HCL-to-UCLID5 translation while a Python program handles merging and option selection. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[3] The verification task used SEQ as a reference model and compared it with seven variants of PIPE for functional equivalence. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[4] Control logic for SEQ and PIPE is described in HCL, and using a common representation helps maintain consistency among simulation models, synthesizable hardware descriptions, and formal verification. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[5] HCL2U generates a UCLID5 macro for each HCL signal definition, and the translation is straightforward but not intended to be human-readable. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[6] HCL case expressions are translated into nested if-then-else expressions, and HCL set membership tests are expanded into disjunctions of equality tests. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[7] Because HCL does not require a default case, HCL2U replicates the final then value as the final else value in nested if-then-else translations. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[8] The provided ALU input example translates an HCL signal definition into a UCLID5 macro named gen_aluA() returning common.word_t. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5