Hardware Control Language (HCL)

Tool

Hardware Control Language (HCL) is a simple hardware description language used to describe processor control logic for the SEQ and PIPE Y86-64 microprocessor models. In the cited verification workflow, HCL served as a common source for simulation, synthesis-oriented, and formal-verification artifacts.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

Hardware Control Language (HCL) is a simple hardware description language used to describe the control logic for both the SEQ and PIPE Y86-64 processor implementations. In the cited UCLID5 verification workflow, HCL provided a common representation from which multiple downstream artifacts could be generated, helping keep simulation models, synthesizable hardware descriptions, and formal-verification models consistent.

Role in processor verification

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NEIGHBORHOOD

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RELATIONSHIPS

3 connections

HCL2U Translator ← uses 100% 2e

The HCL2U translator takes HCL descriptions and generates UCLID5 code.

Sequential Reference Model (SEQ) ← uses 100% 1e

The control logic for SEQ is described in HCL.

PIPE Pipeline Processor ← uses 100% 1e

The control logic for PIPE is described in HCL.

LINKED ENTITIES

1 links

UCLID5 translation_target The evidence states that HCL control logic was translated into UCLID5 macro definitions and used to generate UCLID5 files for verification tasks.

CITATIONS

8 sources

8 citations — click to expand

[1] HCL is a simple hardware description language for the control logic of SEQ and PIPE. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[2] Using HCL as a common representation maintained consistency among simulation models, synthesizable hardware descriptions, and formal verification. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[3] The verification workflow compared SEQ as a reference Y86-64 implementation against seven PIPE variants for functional equivalence. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[4] Translators existed from HCL to C, Verilog, and an earlier version of UCLID. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[5] HCL2U translates HCL signal definitions into UCLID5 macro definitions, and a Python program performs merging and option selection in the generation flow. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[6] HCL files contain signal definitions, and HCL supports case expressions and set-membership tests. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[7] HCL case expressions are translated to nested UCLID5 if-then-else expressions, set membership is expanded to equality disjunctions, and HCL does not require a default case. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[8] The cited ALU-input example selects among valA, valC, +8, and -8 based on the current instruction code. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5