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Y86-64

Concept

Y86-64 is an instruction-set architecture used in the Bryant–O’Hallaron textbook, with sequential and pipelined processor implementations used as subjects for formal verification. Its programmer-visible state includes registers, condition codes, the program counter, data memory, and an exception status word.

First seen 5/26/2026
Last seen 5/26/2026
Evidence 7 chunks
Wiki v1

WIKI

Overview

Y86-64 is an instruction set presented in the Bryant–O’Hallaron textbook, together with a pipelined implementation of a Y86-64 processor. The same textbook also defines homework modifications to that pipeline, yielding seven pipeline variants used in a formal-verification study. [Y86-64 instruction set and variants]

Programmer-visible state

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NEIGHBORHOOD

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RELATIONSHIPS

7 connections
Sequential Reference Model (SEQ) ← part of 95% 2e
SEQ is the sequential reference implementation of the Y86-64 ISA.
Bryant-O'Hallaron Computer Systems Textbook ← introduces 100% 2e
The Bryant-O'Hallaron textbook presents the Y86-64 instruction set and pipelined implementation.
Intel64 (x86-64) ISA derived from → 100% 2e
Y86-64 is modeled after the Intel64 (x86-64) instruction set but is much simpler.
UCLID5 ← evaluates 100% 1e
UCLID5 is used to formally verify the Y86-64 pipelined microprocessor designs.
PIPE Pipeline Processor ← part of 95% 1e
PIPE is the pipelined implementation of the Y86-64 instruction set.
Register File ← part of 100% 1e
The Y86-64 ISA includes a register file with 15 program registers.
Condition Codes ← part of 100% 1e
The Y86-64 ISA has three bits of condition codes for controlling conditional branches.

LINKED ENTITIES

2 links
UCLID5 used_for_formal_verification The evidence describes generating UCLID5 models and verification scripts for Y86-64 processor verification.
Z3 smt_solver_used_in_verification The evidence states that UCLID5 invokes SMT solvers and that the verification work used the Z3 solver.

CITATIONS

10 sources
10 citations — click to expand
[1] Y86-64 instruction set and variants Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[2] Programmer-visible state Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[3] SEQ execution flow Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[4] SEQ as reference Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[5] PIPE structure Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[6] PIPE variants Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[7] HCL control logic Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[8] UCLID5 generation Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[9] Functional equivalence task Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[10] UCLID5 verification process Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5