Bryant-O'Hallaron Computer Systems Textbook
PaperThe Bryant-O’Hallaron textbook is cited as the source for the Y86-64 instruction set, its sequential SEQ processor, and a five-stage pipelined PIPE implementation. In the cited verification report, the textbook’s Y86-64 material serves as the basis for formal verification of seven PIPE variants against SEQ.
First seen 5/26/2026
Last seen 5/26/2026
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Overview
The Bryant-O’Hallaron textbook presents the Y86-64 instruction set and a pipelined implementation of a Y86-64 processor. It also includes homework problems that modify the pipeline, yielding a total of seven variants considered in a later formal verification report. [C1]
Y86-64 architecture coverage
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3 connectionsThe Bryant-O'Hallaron textbook presents the Y86-64 instruction set and pipelined implementation.
The Bryant-O'Hallaron textbook presents the PIPE pipelined processor implementation of Y86-64.
The Bryant-O'Hallaron textbook introduces SEQ as the sequential reference model for Y86-64.
CITATIONS
12 sources12 citations — click to expand
[1] Textbook presents Y86-64, a pipelined implementation, and homework modifications yielding seven variants Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[2] Y86-64 programmer-visible state includes registers, condition codes, PC, data memory, and an exception status word Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[3] Y86-64 instruction encodings range from one to ten bytes and include instruction, register, and constant fields Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[4] Function codes specify ALU operations, branch conditions, and conditional move conditions; iaddq is an optional homework instruction Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[5] Y86-64 has CISC-like features including variable-length encodings, condition-code side effects, and stack-based calls Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[6] Y86-64 has RISC-like simplifications including register-only arithmetic/logical operations and simple base-plus-displacement addressing Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[7] SEQ executes a complete Y86-64 instruction per cycle and uses HCL-described control logic Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[8] SEQ cycle flow fetches bytes, reads registers, uses the ALU, accesses memory, writes registers, and updates the PC Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[9] PIPE is a five-stage Y86-64 pipeline with pipeline registers and hazard-handling logic Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[10] PIPE variants include STD, FULL, STALL, and other variants modifying instructions, forwarding, branch prediction, or register ports Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[11] Verification uses SEQ as the Y86-64 reference and checks functional equivalence against all seven PIPE variants Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[12] HCL translation supports consistency across simulation models, synthesizable hardware descriptions, and formal verification Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5