UCLID5 Pipeline Register Definition

CodeArtifact

A UCLID5 model fragment for a pipelined Y86-64 microprocessor pipeline register. On each step, the register selects one of four behaviors, in priority order: initialize, stall, inject a bubble, or load its input.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 1 chunks

Wiki v1

WIKI

UCLID5 Pipeline Register Definition

Overview

The UCLID5 Pipeline Register Definition is the pipeline-register update logic shown as Figure 12 in Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5. The figure defines how a pipeline register updates its output value val on each step: it can initialize, stall, inject a bubble, or load its input. [pipeline-register-step-semantics]

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

2 connections

UCLID5 part of → 100% 1e

The UCLID5 pipeline register definition is a code artifact used in the UCLID5 verification framework.

Instruction Pipeline Register implements → 100% 1e

The UCLID5 pipeline register definition implements the pipeline registers used in the PIPE model.

CITATIONS

7 sources

7 citations — click to expand

[1] pipeline-register-step-semantics Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[2] pipeline-register-visible-interface Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[3] pipeline-register-priority Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[4] pipeline-flushing Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[5] bubble-injection-usage Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[6] verification-context Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[7] model-size Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5