UCLID5 Pipeline Register Definition

Overview

The UCLID5 Pipeline Register Definition is the pipeline-register update logic shown as Figure 12 in Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5. The figure defines how a pipeline register updates its output value val on each step: it can initialize, stall, inject a bubble, or load its input. [pipeline-register-step-semantics]

Interface elements visible in the definition

The visible portion of the definition includes word-typed data inputs in_value, empty_value, init_value, and old_value, and returns val : word_t. [pipeline-register-visible-interface]

in_value : word_t,
empty_value : word_t,
init_value : word_t,
old_value : word_t)
  returns (val : word_t)
{
  if (initialize) {
     val = init_value;
  } else {
     if (stall) {
      val = old_value;
     } else {
      if (bubble) {
        val = empty_value;
      } else {
        val = in_value;
      }
     }
  }
}

Update priority

The definition implements a nested-priority selection among possible register actions: [pipeline-register-priority]

1. If initialize is true, val becomes init_value.
2. Otherwise, if stall is true, val remains old_value.
3. Otherwise, if bubble is true, val becomes empty_value.
4. Otherwise, val becomes in_value.

This ordering means that initialization takes precedence over stalling, stalling takes precedence over bubble injection, and bubble injection takes precedence over normal input loading. [pipeline-register-priority]

Role in pipeline flushing

The same evidence describes a flushing mechanism added to the PIPE framework for Burch-Dill verification. Flushing stops fetching new instructions while allowing instructions already in the pipeline to complete, and it is implemented by injecting a bubble into the decode stage each cycle until the pipeline is empty. [pipeline-flushing]

Bubble injection dynamically introduces nop instructions and sets the status register to SBUB, indicating a pipeline bubble. The text notes that this bubble-injection capability was already part of the pipeline control logic for normal execution cases, such as waiting until a return address can be popped from the stack during a ret instruction. [bubble-injection-usage]

Verification context

The pipeline-register definition appears in a UCLID5 model used for formal verification of pipelined Y86-64 microprocessors. In that context, the PIPE framework was extended with a force_flush input control signal, while the SEQ framework was extended with a proj_impl input signal to load architectural state from PIPE before running one SEQ step. [verification-context]

The source reports that each PIPE variant required around 650 lines of UCLID5 code for the pipeline framework, plus 930–1030 generated lines from HCL files. [model-size]