University of California, Berkeley
OrganizationUniversity of California, Berkeley is technically relevant in the supplied evidence as the origin institution for the RISC-V project and as one institution in the development lineage of UCLID5, a formal-verification tool used for modeling and verifying hardware and software systems.
First seen 5/25/2026
Last seen 6/11/2026
Evidence 3 chunks
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Technical role in the provided evidence
University of California, Berkeley appears in the supplied technical evidence in two computer-systems contexts: the origin of the RISC-V project and the development lineage of UCLID5.
RISC-V origin
NEIGHBORHOOD
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3 connectionsRISC-V was originally developed at the University of California, Berkeley.
Krste Asanovic is a professor at UC Berkeley who initiated the RISC-V project.
David Patterson is a professor at UC Berkeley who co-initiated the RISC-V project.
CITATIONS
6 sources6 citations — click to expand
[1] The RISC-V project originated from the Computer Science Division at the University of California, Berkeley and was initiated in 2010 under Professors Krste Asanović and David Patterson with their team. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[2] The first RISC-V specifications were made public in 2011, and RISC-V International was formed in 2015 to further standardization and adoption of the RISC-V ISA. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[3] RISC-V is described as a modular ISA consisting of alternative base parts and optional extensions developed collectively by industry, the research community, and educational institutions. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[4] UCLID5 is described as the most recent in a series of formal-verification tools developed at Carnegie Mellon University and the University of California, Berkeley, and as providing both a modeling language and a command language for verification scripts. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[5] UCLID5 supports models combining synchronous hardware and software, representing hardware as state machines and software as sequences of state-updating operations. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[6] UCLID5 supports hardware-modeling data types including uninterpreted values, integers, bit vectors, enumerated types, Booleans, tuples and records, and arrays, and allows these types to be combined flexibly. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5