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University of California, Berkeley

Organization WIKI v2 · 5/28/2026

University of California, Berkeley is technically relevant in the supplied evidence as the origin institution for the RISC-V project and as one institution in the development lineage of UCLID5, a formal-verification tool used for modeling and verifying hardware and software systems.

Technical role in the provided evidence

University of California, Berkeley appears in the supplied technical evidence in two computer-systems contexts: the origin of the RISC-V project and the development lineage of UCLID5.

RISC-V origin

The RISC-V project is described as originating from the Computer Science Division at the University of California, Berkeley. The project was initiated in 2010 under the leadership of Professors Krste Asanović and David Patterson, together with their team.[1]

The evidence further states that the first RISC-V specifications were made public in 2011 and that RISC-V International was formed in 2015 to support standardization and adoption of the RISC-V instruction set architecture.[2]

Technically, RISC-V is described as a modular instruction set architecture made from alternative base parts plus optional extensions. The base ISA and extensions are developed through a collective effort involving industry, the research community, and educational institutions.[3]

UCLID5 formal-verification lineage

University of California, Berkeley is also cited as one of the institutions associated with the development lineage of UCLID5. The cited report describes UCLID5 as the most recent in a series of formal-verification tools developed at Carnegie Mellon University and the University of California, Berkeley.[4]

UCLID5 provides both a modeling language for describing the system to be verified and a command language for writing verification scripts. In the cited microprocessor-verification use case, the modeled system combines a pipelined microprocessor with a sequential reference implementation, while the verification script specifies initialization, operation, and verification-condition checks for Burch-Dill correspondence checking.[4]

Modeling capabilities noted in the evidence

The evidence describes UCLID5 as supporting models that combine synchronous hardware and software. Hardware is represented as state machines that compute a next state from the current state and then transition to it; software is represented as sequences of operations that update system state.[5]

For hardware modeling, UCLID5 supports multiple data types, including uninterpreted values, integers, bit vectors, enumerated types, Booleans, tuples and records, and arrays. The report notes that these types can be combined flexibly, such as by defining functions over multiple argument types or arrays over arbitrary index types.[6]

Relationship summary

Within the provided evidence, University of California, Berkeley is technically significant as the institution where RISC-V originated and as an institutional contributor to the UCLID5 formal-verification tool lineage.

CITATIONS

6 sources
6 citations
[1] The RISC-V project originated from the Computer Science Division at the University of California, Berkeley and was initiated in 2010 under Professors Krste Asanović and David Patterson with their team. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[2] The first RISC-V specifications were made public in 2011, and RISC-V International was formed in 2015 to further standardization and adoption of the RISC-V ISA. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[3] RISC-V is described as a modular ISA consisting of alternative base parts and optional extensions developed collectively by industry, the research community, and educational institutions. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[4] UCLID5 is described as the most recent in a series of formal-verification tools developed at Carnegie Mellon University and the University of California, Berkeley, and as providing both a modeling language and a command language for verification scripts. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[5] UCLID5 supports models combining synchronous hardware and software, representing hardware as state machines and software as sequences of state-updating operations. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[6] UCLID5 supports hardware-modeling data types including uninterpreted values, integers, bit vectors, enumerated types, Booleans, tuples and records, and arrays, and allows these types to be combined flexibly. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

VERSION HISTORY

v2 · 5/28/2026 · gpt-5.5 (current)
v1 · 5/25/2026 · gpt-5.5