Term-Level Modeling
ConceptTerm-level modeling is an abstraction style used in formal verification, where data values can be treated as uninterpreted terms and operations can be represented by uninterpreted functions. In the UCLID5-based verification of pipelined Y86-64 microprocessors, this style is described as suitable for Burch-Dill correspondence checking and for modeling hardware blocks whose detailed functionality is unnecessary as long as they behave consistently across the pipeline and the sequential reference model.
WIKI
Overview
Term-level modeling is a formal-verification modeling style in which values may be represented as uninterpreted terms. In the UCLID5 setting described for verifying pipelined Y86-64 microprocessors, uninterpreted data is identified as suitable for the term-level modeling demonstrated by Burch and Dill. These terms can be tested for equality, and they can be used together with uninterpreted functions whose behavior is arbitrary but consistent. [term-level-uninterpreted]
Role in hardware verification
NEIGHBORHOOD
No graph connections found for this entity yet. It may appear in future ingestion runs.
explore full graph →