Overview

Brian Campbell is mentioned in the paper Randomized Testing of RISC-V CPUs using Direct in the context of formal ISA models, constraint-solving-based test generation, and TestRIG's future development path.

Work on Sail-based verification tooling

The paper states that previous CHERI work used tests generated from a formal CHERI-MIPS ISA model written in L3, compiled from L3 to HOL4, with constraint solving used to generate instruction sequences that reach desired states without triggering undefined behavior. It then notes that the same approach had been applied to the CHERI ARM Morello instruction set starting from a Sail model.

In that context, the paper identifies Brian Campbell as "a key contributor to this work." It further reports that Campbell had begun work on a Sail-OCaml VEngine with direct access to the data structures of the Sail RISC-V model.

Technical significance

According to the paper, direct access from the Sail-OCaml VEngine to the Sail RISC-V model's data structures eliminates independent encodings in the VEngine. The authors expected this direction to be extended toward automated generation of templates that target specific deep states in the architectural model using constraint solving.