Verification Engine (VEngine)

Concept

In TestRIG, the verification engine is represented by QCVEngine, a Haskell QuickCheck-based engine that generates, compares, and shrinks Direct Instruction Injection instruction sequences and checks returned RVFI traces for equivalence.

First seen 5/27/2026

Last seen 6/2/2026

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Overview

A Verification Engine (VEngine) in the TestRIG context is exemplified by QCVEngine, described as the TestRIG Verification Engine. QCVEngine leverages Haskell’s QuickCheck library and uses the simplicity of Direct Instruction Injection (DII) execution to generate, compare, and shrink instruction sequences. DII decouples the instruction stream from control flow, allowing QCVEngine to use unmodified QuickCheck utilities for these tasks.

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RELATIONSHIPS

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TestRIG ← uses 100% 7e

TestRIG uses a modular Verification Engine (VEngine) to stimulate implementations and compare traces.

Brian Campbell ← part of 80% 1e

Brian Campbell has begun work on a Sail-OCaml VEngine with direct access to the Sail RISC-V model data structures.

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CITATIONS

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[1] QCVEngine is described as the TestRIG Verification Engine and leverages Haskell’s QuickCheck library. Randomized Testing of RISC-V CPUs using Direct

[2] Because DII decouples the instruction stream from control flow, QCVEngine can use unmodified QuickCheck utilities to generate, compare, and shrink instruction sequences. Randomized Testing of RISC-V CPUs using Direct

[3] The QCVEngine checking function sends a list of instructions over two DII sockets, collects RVFI traces, asserts that they match, and returns the result. Randomized Testing of RISC-V CPUs using Direct

[4] QCVEngine provides arbitrary instruction-sequence generators, targeted instruction-subset generators, and template-based generators for deeper states such as virtual-memory mappings and cache conflicts. Randomized Testing of RISC-V CPUs using Direct

[5] QCVEngine has been used to replay recorded test-suite examples, including riscv-tests and RISCV-DV, with full trace-equivalence checking and shrinking. Randomized Testing of RISC-V CPUs using Direct

[6] The initial QCVEngine generators are described as rudimentary, with virtual memory, cache testing, and floating-point operations identified as areas for richer directed-random templates. Randomized Testing of RISC-V CPUs using Direct

[7] Future TestRIG memory-concurrency testing would require a more advanced verification engine that checks RVFI traces not only for equivalence but also against higher-level memory-model semantics. Randomized Testing of RISC-V CPUs using Direct