Sail RISC-V Model

Tool

The Sail RISC-V Model is an architectural model used as a reference in RISC-V processor testing workflows. Evidence describes it being used for coverage measurement across RV32IMC and RV64IMAFDCZicsr configurations, with traces from riscv-tests and RISCV-DV replayed or run against the model, and as a data-structure source for a proposed Sail-OCaml VEngine in TestRIG-related work.

First seen 5/27/2026

Last seen 5/30/2026

Evidence 4 chunks

Wiki v1

WIKI

Overview

The Sail RISC-V Model is referenced as an architectural model for RISC-V used in model-based and randomized CPU testing. In the cited TestRIG work, the model is used as the object whose instruction and register coverage is measured for different RISC-V architecture configurations.

Coverage use in testing

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NEIGHBORHOOD

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RELATIONSHIPS

6 connections

TestRIG ← uses 100% 3e

TestRIG uses the Sail RISC-V model as a reference model for tandem verification.

RISC-V implements → 100% 3e

The Sail RISC-V model is a formal model of the RISC-V architecture.

Sail Language uses → 100% 2e

The Sail RISC-V model is written in the Sail language.

CHERI implements → 90% 2e

The Sail RISC-V model has been extended to include CHERI.

RVFI-DII uses → 100% 1e

The Direct Instruction Injection interface was added to the Sail RISC-V formal model.

sailcov uses → 90% 1e

sailcov measures coverage of the Sail RISC-V model execution.

LINKED ENTITIES

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TestRIG USES Extracted graph relationship

Sail Language USES Extracted graph relationship

RISC-V IMPLEMENTS Extracted graph relationship

RVFI-DII USES Extracted graph relationship

sailcov USES Extracted graph relationship

CITATIONS

8 sources

8 citations — click to expand

[1] The Sail RISC-V Model is used to measure coverage for RV32IMC and RV64IMAFDCZicsr configurations, including specified instruction extensions and register classes. Randomized Testing of RISC-V CPUs using Direct

[2] For riscv-tests, coverage is measured by running test binaries on the Sail RISC-V model. Randomized Testing of RISC-V CPUs using Direct

[3] For RISCV-DV, Spike-produced traces are replayed through RVFI-DII while measuring Sail RISC-V model coverage. Randomized Testing of RISC-V CPUs using Direct

[4] For QCVEngine, the cited experiment configured two architecture strings and ran 500 sequences of each generator. Randomized Testing of RISC-V CPUs using Direct

[5] The TestRIG paper describes a Sail-OCaml VEngine with direct access to the data structures of the Sail RISC-V model, eliminating independent encodings in the VEngine. Randomized Testing of RISC-V CPUs using Direct

[6] The authors expected the Sail-OCaml VEngine approach to support automated generation of templates targeting deep architectural-model states using constraint solving. Randomized Testing of RISC-V CPUs using Direct

[7] The TestRIG paper describes model-based shrinking where any changed trace that still diverges is kept. Randomized Testing of RISC-V CPUs using Direct

[8] The coverage discussion references the sailcov repository. Randomized Testing of RISC-V CPUs using Direct