Skip to content
STIMSMITH

Sail RISC-V Model

Tool WIKI v1 · 5/27/2026

The Sail RISC-V Model is an architectural model used as a reference in RISC-V processor testing workflows. Evidence describes it being used for coverage measurement across RV32IMC and RV64IMAFDCZicsr configurations, with traces from riscv-tests and RISCV-DV replayed or run against the model, and as a data-structure source for a proposed Sail-OCaml VEngine in TestRIG-related work.

Overview

The Sail RISC-V Model is referenced as an architectural model for RISC-V used in model-based and randomized CPU testing. In the cited TestRIG work, the model is used as the object whose instruction and register coverage is measured for different RISC-V architecture configurations.

Coverage use in testing

The model is used to measure coverage for at least two RISC-V architecture strings:

  • RV32IMC: coverage includes the Sail RISC-V model coverage of the I, M, and C extension instructions, as well as general-purpose registers.
  • RV64IMAFDCZicsr: coverage includes I, M, A, F, D, C, and CSR instructions, as well as general-purpose and floating-point registers.

The evidence describes multiple ways of feeding tests or traces into this coverage workflow:

  • For riscv-tests, coverage is measured by running the test binaries on the Sail RISC-V model.
  • For RISCV-DV, traces are produced from the Spike simulator executing the tests, then replayed through RVFI-DII while measuring coverage of the Sail RISC-V model.
  • For QCVEngine, the cited experiment configures the tool with the two architecture strings and runs 500 sequences of each generator.

Role in TestRIG-oriented model-based testing

The TestRIG paper frames its testing as model-based testing and describes shrinking and simplification of instruction traces: changes are safe to try because any changed trace that still diverges is kept. The same section discusses collecting human-readable traces as regression tests for previous counterexamples.

The Sail RISC-V Model also appears in the paper's discussion of future TestRIG directions. The authors report that Brian Campbell had begun work on a Sail-OCaml VEngine with direct access to the data structures of the Sail RISC-V model. The stated benefit is eliminating independent encodings in the VEngine. The authors also expected this approach to support automated generation of templates targeting deep architectural-model states using constraint solving.

Related tooling and interfaces

  • RVFI-DII is used in the RISCV-DV coverage workflow: Spike-generated traces are replayed through RVFI-DII while Sail RISC-V model coverage is measured.
  • sailcov is referenced by the paper in the coverage discussion via a repository link.
  • TestRIG is the surrounding randomized, model-based testing context in which the Sail RISC-V Model is used for coverage and future VEngine integration discussions.

LINKED ENTITIES

5 links
TestRIG USES
Sail Language USES
RISC-V IMPLEMENTS
RVFI-DII USES
sailcov USES

CITATIONS

8 sources
8 citations
[1] The Sail RISC-V Model is used to measure coverage for RV32IMC and RV64IMAFDCZicsr configurations, including specified instruction extensions and register classes. Randomized Testing of RISC-V CPUs using Direct
[2] For riscv-tests, coverage is measured by running test binaries on the Sail RISC-V model. Randomized Testing of RISC-V CPUs using Direct
[3] For RISCV-DV, Spike-produced traces are replayed through RVFI-DII while measuring Sail RISC-V model coverage. Randomized Testing of RISC-V CPUs using Direct
[4] For QCVEngine, the cited experiment configured two architecture strings and ran 500 sequences of each generator. Randomized Testing of RISC-V CPUs using Direct
[5] The TestRIG paper describes a Sail-OCaml VEngine with direct access to the data structures of the Sail RISC-V model, eliminating independent encodings in the VEngine. Randomized Testing of RISC-V CPUs using Direct
[6] The authors expected the Sail-OCaml VEngine approach to support automated generation of templates targeting deep architectural-model states using constraint solving. Randomized Testing of RISC-V CPUs using Direct
[7] The TestRIG paper describes model-based shrinking where any changed trace that still diverges is kept. Randomized Testing of RISC-V CPUs using Direct
[8] The coverage discussion references the sailcov repository. Randomized Testing of RISC-V CPUs using Direct