Architectural Model
ConceptAn architectural model is an architecture-specific declarative description that, together with a test-template and (typically) testing knowledge, drives model-based generation of processor verification tests. In Genesys-Pro it is kept separate from the generic generation engine and supplies a declarative processor description plus design-specific testing knowledge used as hard and soft constraints in constraint-satisfaction-based test generation. In Threadmill, an on-platform post-silicon exerciser, the architectural model is one of the inputs that the off-line builder converts into simple data structures embedded in the exerciser image, and it is consulted while generating, executing, and checking random test-cases on silicon or accelerator platforms.
First seen 5/26/2026
Last seen 7/28/2026
Evidence 14 chunks
Wiki v3
WIKI
Definition
An architectural model is the architecture-specific model maintained separately from a generic test-generation engine. It contains processor-specific information, principally a declarative description of a particular processor architecture and a database of testing knowledge relevant to that processor. [Architectural-model contents in Genesys-Pro]
Role in model-based test generation (Genesys-Pro)
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3 connectionsThreadmill uses an architectural model as part of its input for test generation.
Genesys-Pro relies on an architectural model that contains processor-specific information
The testing knowledge database is part of the architectural model
LINKED ENTITIES
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16 sources16 citations — click to expand
[1] An architectural model is the architecture-specific model kept separate from a generic generation engine and contains a declarative processor description and design-specific testing knowledge. Genesys-Pro: innovations in test program generation for functional processor verification
[2] Genesys-Pro formulates and solves a separate constraint problem for each test instruction based on constraints from the architectural description, testing knowledge, and test-template directives. Genesys-Pro: innovations in test program generation for functional processor verification
[3] Separating the model from the engine permits rapid development, easy maintenance, and lets users maintain tool versions for several designs and follow-ons. Genesys-Pro: innovations in test program generation for functional processor verification
[4] The architectural model's architecture-dependent knowledge includes a declarative processor description and design-specific testing knowledge to raise coverage of events random tests tend to miss. Genesys-Pro: innovations in test program generation for functional processor verification
[5] The modeling framework's high-level building blocks and constraint-based representation are especially useful for VLIW architectures and complex address-translation mechanisms. Genesys-Pro: innovations in test program generation for functional processor verification
[6] Instruction attributes include an opcode plus attributes describing the resources used (data, family, address, units), and relations between attributes are expressed as constraints such as source.address = base.data + displacement.data and base.address != target.address. Genesys-Pro: innovations in test program generation for functional processor verification
[7] Simple equations can be stated directly in the model, while relations with more complex semantics refer to an external C++ implementation provided by the modeling engineer. Genesys-Pro: innovations in test program generation for functional processor verification
[8] Instruction-specific testing knowledge can bias generation toward rare events, such as making data(Ra) + data(Rb) = 0 more likely for an Add instruction. Genesys-Pro: innovations in test program generation for functional processor verification
[9] Testing knowledge such as PageCross constrains attribute values (e.g., forcing an address to cross a page boundary) and is often accumulated and reused across follow-on designs. Genesys-Pro: innovations in test program generation for functional processor verification
[10] Constraints originating from the architectural description are typically mandatory hard constraints, while testing-knowledge and test-template constraints may be set as mandatory or nonmandatory soft constraints. Genesys-Pro: innovations in test program generation for functional processor verification
[11] In Threadmill the architectural model is an input alongside the test-template, testing knowledge, and system topology, used to drive post-silicon test generation. Threadmill: a post-silicon exerciser for multi-threaded processors
[12] A Threadmill builder runs off-line to convert the test-template and architectural model into data structures embedded into the exerciser image, so the running exerciser does not access files or databases. Threadmill: a post-silicon exerciser for multi-threaded processors
[13] The exerciser image consists of a thin OS-like services layer, a representation of the test-template, architectural model, and system configuration as data structures, and fixed test-template-independent exercising code; it repeatedly generates a random test-case, executes it, and checks its results. Threadmill: a post-silicon exerciser for multi-threaded processors
[14] Threadmill avoids constraint satisfaction techniques and reference models for both test generation and on-platform checking, in contrast to Genesys-Pro. Threadmill: a post-silicon exerciser for multi-threaded processors
[15] A unified pre- and post-silicon verification methodology maps line-items of the verification plan to multiple target platforms and uses similar test-template languages so pre- and post-silicon tools produce similar (though not identical) test-cases from the same template. A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation
[16] Threadmill's test-template language omits constructs that require long generation time, and many Genesys-Pro testing-knowledge items are not used, to keep Threadmill's generation simple and fast for the on-platform and acceleration environments. Threadmill: a post-silicon exerciser for multi-threaded processors