Threadmill

Tool

First seen 7/9/2026

Last seen 7/28/2026

Evidence 22 chunks

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Test Template uses → 100% 4e

Threadmill takes test-templates as main input to direct test generation.

Architectural Model uses → 100% 4e

Threadmill uses an architectural model as part of its input for test generation.

Genesys-Pro ← compares with 95% 4e

Threadmill is compared to GenesysPro as the pre-silicon counterpart tool.

Unified Pre- and Post-Silicon Verification Methodology implements → 100% 3e

Threadmill was developed to support a unified pre- and post-silicon verification methodology.

Static Branch Generation implements → 95% 2e

Threadmill uses a static test generator for branch generation, without a reference model.

Dual-Pass Branch Generation implements → 95% 2e

Threadmill uses a dual-pass technique to finalize branch instruction construction during test execution.

Illegal Instruction Interrupt Handler for Branch Completion implements → 95% 2e

Threadmill places an illegal instruction in the test stream to defer branch construction to runtime via an interrupt handler.

Off-Platform Floating-Point Operand Pre-Generation implements → 100% 2e

Threadmill pre-generates floating-point operands off-platform and embeds them in the exerciser image.

Joint Random Seed for Distributed Generation implements → 100% 2e

Threadmill uses a shared random seed to coordinate distributed generation decisions across threads.

IBM POWER7 evaluates → 100% 2e

Threadmill was used in the verification and bring-up of IBM POWER7.

Exercisers on Accelerators part of → 90% 2e

Threadmill was used as an exerciser in the EoA phase.

Concurrent Multi-Threaded Test-Case Generation implements → 100% 2e

Threadmill generates multi-threaded test-cases in a concurrent, distributed manner.

post-silicon validation implements → 100% 2e

Threadmill is designed specifically for post-silicon validation of multi-threaded processors.

FPgen uses → 100% 2e

Threadmill uses FPgen off-line to pre-generate interesting floating-point operand data.

POWER7 evaluates → 100% 2e

Threadmill was used in the verification of the POWER7 processor.

Verification Plan uses → 90% 2e

Threadmill's test generation is guided by a verification plan expressed via test templates.

Floating-Point Unit Verification evaluates → 90% 2e

Threadmill evaluates floating-point unit verification by generating FP instructions with interesting operand values.

Memory Coherence Testing evaluates → 90% 2e

Threadmill tests hardware memory coherence mechanisms through concurrent multi-threaded test generation.

Bare-Metal Execution implements → 100% 2e

Threadmill is explicitly described as a bare-metal exerciser.

On-Platform Test Generation implements → 100% 2e

Threadmill generates tests on the silicon platform rather than off-line.

Pseudo-Random Test Generation implements → 100% 2e

Threadmill uses a simple and fast pseudo-random generation engine.

Multi-Pass Consistency Checking implements → 100% 2e

Threadmill uses multi-pass consistency checking to detect bugs without a reference model.

Constraint Satisfaction Problem mentions → 90% 2e

Threadmill explicitly avoids using constraint satisfaction techniques, contrasting with pre-silicon tools.

Load/Store Instruction Generation implements → 90% 2e

Threadmill generates load/store instructions as part of its multi-threaded test-case generation.

Reference Model mentions → 95% 2e

Threadmill explicitly does not use a reference model, which is commonly used in pre-silicon verification.

Random Test Program Generation implements → 95% 2e

Threadmill implements random test program generation as its core engine.

Write-Write Collision mentions → 90% 2e

Threadmill explicitly forbids write-write collisions on checked memory areas during consistency checking.

A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation ← introduces 100% 2e

The paper introduces the Threadmill tool for post-silicon validation.

Verification Plan depends on → 95% 1e

Threadmill was developed to support a verification process guided by a verification plan.

Joint Random Collision Generation implements → 95% 1e

Threadmill uses joint random collision generation to produce colliding memory accesses among threads.

Shared Memory Multiprocessor Assertion Testing implements → 85% 1e

Threadmill supports assertion-based tests for shared memory multiprocessors, as exemplified by Collier's tests.

Memory Trace for Debug uses → 85% 1e

Threadmill saves random seeds in a limited memory trace to support test-case recreation for debugging.

Hardware Acceleration Platform depends on → 80% 1e

Threadmill was developed to also operate on hardware acceleration platforms.

Address Translation Path Generation mentions → 80% 1e

The paper mentions future work to leverage address translation path generation as a future enhancement for Threadmill.

bare-metal exerciser implements → 100% 1e

Threadmill is implemented as a bare-metal exerciser operating directly on silicon.

Test Template Language uses → 100% 1e

Threadmill uses a test-template language very similar to GenesysPro's language.

Testing Knowledge uses → 90% 1e

Threadmill uses testing knowledge, though fewer items than GenesysPro.

multi-pass comparison checking implements → 90% 1e

Threadmill implements multi-pass comparison checking as a partial replacement for reference model checking.

Static Test Generation implements → 95% 1e

Threadmill's generation is static, without the use of a reference model.

Threadmill: A Post-Silicon Exerciser for Multi-Threaded Processors ← introduces 100% 1e

The paper introduces Threadmill as a bare-metal exerciser targeting multi-threaded processors.