Bare-metal exerciser

Concept

A bare-metal exerciser is a post-silicon stimuli-generation and verification tool that runs directly on the silicon design under verification (DUV) without the support of an operating system. It continuously generates test-cases, executes them, and checks their results in an endless loop, providing a self-contained, long-running solution well suited to the lengthy loading and initialization times of silicon platforms.

First seen 7/28/2026

Last seen 7/28/2026

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Bare-metal exerciser

Definition

A bare-metal exerciser is a type of exerciser used in post-silicon validation that operates directly on the silicon itself, without relying on an operating system. It is a self-contained verification tool that generates test-cases, executes them on the design under verification (DUV), checks their results, and provides the OS-like services required by those test-cases ^[1]^[2].

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post-silicon validation ← uses 90% 2e

Post-silicon validation relies on exercisers as long-running solutions.

Threadmill ← implements 100% 1e

Threadmill is implemented as a bare-metal exerciser operating directly on silicon.

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Threadmill IMPLEMENTS Extracted graph relationship

post-silicon validation USES Extracted graph relationship

CITATIONS

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[1] A bare-metal exerciser operates on the silicon itself without the support of an operating system. A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation

[2] An exerciser is a self-contained solution that generates test-cases, runs them, does the checking, and contains OS services required by the test-cases; it runs in an endless loop and is only loaded once on the DUV. A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation

[3] Silicon platforms suffer from long loading and initialization time (e.g., over a minute for a 10,000-instruction test-case), leading to very low execution utilization and motivating endless-loop exercisers. A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation

[4] The exerciser image consists of a thin OS-like layer for bare-metal execution, simple data structures representing the test-template, architectural model and configuration, and fixed test-template-independent exercising code; once loaded it indefinitely generates, executes, and checks random test-cases. A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation

[5] Post-silicon exercisers must be simple, run without an OS or I/O support, and keep the ratio of generation/checking time to execution time low; embedding a reference model is generally avoided because its complexity reduces platform utilization. A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation

[6] Without a reference model, Threadmill substitutes partial replacements such as reloading registers and reserving registers with interesting values (e.g., for data-oriented events like divide-by-zero) while ensuring those registers are not modified during the test. A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation

[7] Pre-silicon generators use a reference model to maintain an accurate view of processor state and bias stimuli toward interesting events; this is not practical inside a bare-metal exerciser. A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation

[8] Threadmill is a directable, bare-metal exerciser with a simple and fast static test-generation engine that does not rely on a reference model. A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation

[9] Running exercisers on accelerators provides coverage feedback that is merged into project coverage reports and used to harvest high-quality test-templates for the silicon bring-up team. A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation

[10] Coverage can be measured for a post-silicon exerciser by running it on an acceleration platform, which provides the observability not available on silicon. A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation