A verification plan is a structured artifact in hardware and system verification that documents the design under verification, its functional specification, coverage goals, and the verification activities (and often correction activities) required across development phases. In assertion-based functional verification (ABV) it bundles the design description, functional and code coverage targets, and the assertions that check for errors and measure coverage. At the system level it is cast as a sequential decision problem that selects verification and correction activities across development phases. Automatic test-program generators such as IBM Genesys and Genesys-Pro are designed to consume the knowledge captured in a verification plan in order to produce functional test programs for microprocessor designs.