Genesys-pro: innovations in test program generation for functional processor verification
Paper“Genesys-pro: innovations in test program generation for functional processor verification” is a 2004 D&T paper cited in later processor-verification literature as an example of instruction-stream/test-program generation using constraint-solving techniques.
First seen 5/24/2026
Last seen 5/30/2026
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Overview
“Genesys-pro: innovations in test program generation for functional processor verification” is a paper on test program generation for functional processor verification. In the available evidence, it appears as reference [1] in the 2020 paper Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study.[C1]
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NEIGHBORHOOD
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11 connectionsThe paper introduces and describes Genesys-Pro
The paper cites Genesys-pro as related work on test program generation.
The paper is authored by Laurent Fournier among others
The paper is authored by Eitan Marcus among others
The paper is authored by Michal Rimon among others
The paper is authored by Allon Adir among others
The paper is authored by Avi Ziv among others
The paper is published by researchers at IBM Research Lab, Haifa
The paper mentions Genesys-Pro as a related model-based test generation approach.
The paper is authored by Michael Vinov among others
The paper is authored by Eli Almog among others
CITATIONS
2 sources2 citations — click to collapse
[1] The paper is cited as “Genesys-pro: innovations in test program generation for functional processor verification,” published in D&T, pages 84–93, in 2004; the visible author list includes E. Marcus, M. Rimon, M. Vinov, and A. Ziv, with a preceding truncated author name ending in “ournier.” Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
[2] The 2020 RISC-V cross-level testing paper discusses instruction stream generation for processor verification and identifies references [1] and [2] as prominent examples using constraint-solving techniques; reference [1] is the Genesys-pro paper. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study