Constraint Solving for Test Generation

Concept

Constraint solving for test generation is an approach in which constraints derived from an architectural or formal model are used to automatically generate instruction sequences that reach desired processor states while avoiding undefined behavior. In the provided evidence, the approach is described in prior CHERI test generation work and as a possible direction for TestRIG-style model-based testing.

First seen 5/30/2026

Last seen 6/3/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

Constraint solving for test generation uses constraints from a model specification to automatically construct tests that satisfy particular architectural conditions. In the processor-testing context described by the evidence, the goal is to generate instruction sequences that reach a desired state while avoiding undefined behavior. Prior CHERI work generated tests from a formal CHERI-MIPS ISA model written in L3, compiled from L3 to HOL4, and then used constraint solving to generate such instruction sequences. The same approach is reported as having been applied to the CHERI ARM Morello instruction set from a Sail model. ^[1]

Role in architecture-level test generation

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RELATIONSHIPS

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Genesys-Pro ← uses 90% 5e

Genesys-Pro uses templates that solve for desired deep states, implying constraint solving.

TestRIG ← uses 75% 1e

Future TestRIG work plans to use constraint solving to automate generation of templates targeting specific deep states.

L3 Specification Language uses → 85% 1e

Previous CHERI work used constraint solving based on tests generated from a formal model written in L3.

LINKED ENTITIES

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Genesys-Pro USES Extracted graph relationship

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CITATIONS

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[1] Prior CHERI work generated tests from a formal CHERI-MIPS ISA model written in L3, compiled from L3 to HOL4, and used constraint solving to automatically generate instruction sequences reaching desired states without undefined behavior. Randomized Testing of RISC-V CPUs using Direct

[2] The constraint-solving approach was also applied to the CHERI ARM Morello instruction set starting from a Sail model. Randomized Testing of RISC-V CPUs using Direct

[3] The TestRIG paper describes future automation of template generation for specific deep states in the architectural model using constraint solving. Randomized Testing of RISC-V CPUs using Direct

[4] IBM’s Genesys-Pro is described as being built on templates used to intelligently solve for desired deep states. Randomized Testing of RISC-V CPUs using Direct

[5] TestRIG includes model-based randomized testing features such as smart shrinking, non-shrinkable sequences, and assertions. Randomized Testing of RISC-V CPUs using Direct