Smart Shrinking

Technique

Smart Shrinking is a counterexample-reduction technique used in randomized RISC-V CPU testing. It augments ordinary QuickCheck list shrinking by transforming instruction sequences, such as propagating produced registers into later operands and applying simplification rules, so failing traces become shorter and easier to diagnose.

First seen 5/30/2026

Last seen 6/2/2026

Evidence 4 chunks

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WIKI

Overview

Smart Shrinking is a technique for simplifying failing instruction sequences after a counterexample has been found during randomized RISC-V CPU testing. In the TestRIG context, a counterexample is found by QCVEngine, after which QuickCheck's built-in list-shrinking can remove instructions and retest the shorter sequence. Smart Shrinking extends this basic approach by not only deleting instructions, but also transforming instructions to simplify the trace while preserving the failing behavior.

How it works

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NEIGHBORHOOD

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RELATIONSHIPS

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QCVEngine ← uses 100% 2e

QCVEngine uses smart shrinking to simplify counterexamples beyond QuickCheck's built-in shrinking.

Test Case Shrinking extends → 95% 1e

Smart shrinking extends test case shrinking by intelligently transforming instructions rather than just eliminating them.

C-Reduce compares with → 70% 1e

C-Reduce is mentioned as an analogue to the automated test-case reduction done in TestRIG via smart shrinking.

QuickCheck extends → 90% 1e

Smart shrinking augments QuickCheck's built-in shrinking with intelligent transformations.

LINKED ENTITIES

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QCVEngine USES Extracted graph relationship

Test Case Shrinking EXTENDS Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] Smart Shrinking augments QuickCheck's built-in shrinking by eliminating instructions and intelligently transforming instruction sequences. Randomized Testing of RISC-V CPUs using Direct

[2] After QCVEngine finds a counterexample, QuickCheck's built-in list-shrinking removes sequences from the list and retests to remove instructions irrelevant to the errant behavior. Randomized Testing of RISC-V CPUs using Direct

[3] Smart Shrinking can propagate an instruction's output register to future input operands, enabling another list-shrinking pass to further reduce a counterexample. Randomized Testing of RISC-V CPUs using Direct

[4] The example sequence for an artificial add-instruction bug is reduced from a longer trace to a two-instruction counterexample by combining built-in list shrinking with Smart Shrinking's register propagation. Randomized Testing of RISC-V CPUs using Direct

[5] Smart Shrinking includes a library of simplifications that eliminate esoteric instructions performing mundane functions so they do not distract from the root cause of a failure. Randomized Testing of RISC-V CPUs using Direct