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Direct Instruction Injection

Concept

A testing interface used by the TestRIG verification framework to inject instructions directly into a RISC-V Design under Verification (DUV) for randomized testing of RISC-V CPUs, including CHERI-enabled variants. It enables high-throughput instruction generation without requiring consistent program control flow.

First seen 5/29/2026
Last seen 7/6/2026
Evidence 16 chunks
Wiki v2

WIKI

Overview

Direct Instruction Injection (DII) is the interface through which TestRIG injects generated instructions into a RISC-V Design under Verification (DUV). It is part of the randomized testing infrastructure used to verify RISC-V CPUs, and it is reused in downstream work that targets CHERI-enabled RISC-V designs.

Role in TestRIG

According to the cited description of TestRIG, the framework interfaces with the DUV via two mechanisms:

  • RISC-V Formal Interface (RVFI) – provides fine-grained visibility into architectural state after each instruction, enabling precise semantic validation.
  • Direct Instruction Injection (DII) – injects instructions into the simulation.
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NEIGHBORHOOD

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RELATIONSHIPS

7 connections
TestRIG ← uses 100% 9e
TestRIG uses the Direct Instruction Injection interface to execute generated instructions on the DUV.
TestRIG ← implements 100% 4e
TestRIG uses Direct Instruction Injection as its core mechanism for injecting instructions into CPU implementations.
UCAM-CL-TR-984 ← uses 100% 3e
Direct Instruction Injection (DII) is used as a protocol for testing RISC-V processors via TestRIG.
QCVEngine ← uses 100% 2e
QCVEngine uses Direct Instruction Injection to decouple instruction stream from control flow.
Randomized Testing of RISC-V CPUs using Direct Instruction Injection ← introduces 100% 2e
The paper introduces Direct Instruction Injection as the core mechanism of TestRIG.
RVFI-DII ← uses 100% 1e
RVFI-DII combines RVFI trace output with Direct Instruction Injection input.
RVFI-DII part of → 100% 1e
Direct Instruction Injection is the input component of the RVFI-DII interface.

LINKED ENTITIES

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TestRIG USES Extracted graph relationship

CITATIONS

8 sources
8 citations — click to expand
[1] TestRIG interfaces with the Design under Verification via the RISC-V Formal Interface (RVFI) and Direct Instruction Injection (DII), executing generated instructions and comparing architectural state against the Sail formal model of the RISC-V ISA. Security-Aware Benchmarks for Performance Exploration of CHERI (DDECS 2026)
[2] A key feature of the DII interface is that instruction execution does not require consistent program control flow, enabling high-throughput instruction generation. Security-Aware Benchmarks for Performance Exploration of CHERI (DDECS 2026)
[3] Communication between TestRIG and the DUV is implemented via standard network sockets, enabling flexible integration with simulators. Security-Aware Benchmarks for Performance Exploration of CHERI (DDECS 2026)
[4] The CHERI-RISC-V VP++ work extends a CHERI RISC-V virtual prototype with DII and RVFI so that TestRIG can drive verification against the CHERI RISC-V Sail reference model, with TestRIG connecting via sockets. CHERI-RISC-V VP++ - ASP-DAC
[5] Verification of CHERI-RISC-V VP++ via TestRIG reported 2+ million test cases executed (including CHERI-specific extensions), 1.8+ billion instructions executed averaging ~860 instructions per test case, and high relevant CHERI-related code coverage. CHERI-RISC-V VP++ - ASP-DAC
[6] DII is listed as the acronym 'Direct Instruction Injection' in the CHERI-RISC-V VP++ thesis. CHERI-RISC-V VP++: A Virtual Prototyping Platform Enabling Fine...
[7] TestRIG's instruction generation infrastructure is repurposed as the basis for security-aware benchmark generation, post-processing generated instruction streams to ensure valid capability usage. Security-Aware Benchmarks for Performance Exploration of CHERI (DDECS 2026)
[8] Direct Instruction Injection underlies the verification flow that relies primarily on QuickCheck's built-in shrinking strategies for failing instruction sequences, augmented with smart shrinking functions that both remove instructions and transform them. TestRIG paper