Register Reuse

Concept

Register reuse is a test-generation tactic used by QCVEngine to bias generated instruction fields toward reusing registers or operands. In the provided evidence, it is used to increase the probability of exposing failures that require multiple operand permutations, while accepting reduced register-number coverage in some areas such as floating-point registers.

First seen 5/27/2026

Last seen 5/27/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

Register reuse refers to a bias in instruction-sequence generation that encourages generated instructions to reuse registers or operands rather than spreading operands uniformly across the full register set. In QCVEngine, this is implemented through tailored instruction-field generators that promote register reuse. [QCVEngine register-reuse generators]

Use in QCVEngine

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

1 connections

QCVEngine ← uses 90% 1e

QCVEngine provides tailored generators that promote register reuse in instruction sequences.

LINKED ENTITIES

1 links

QCVEngine USES Extracted graph relationship

CITATIONS

4 sources

4 citations — click to collapse

[1] QCVEngine register-reuse generators Randomized Testing of RISC-V CPUs using Direct

[2] QCVEngine QuickCheck workflow Randomized Testing of RISC-V CPUs using Direct

[3] Floating-point operand-reuse trade-off Randomized Testing of RISC-V CPUs using Direct

[4] Register-number failure trade-off Randomized Testing of RISC-V CPUs using Direct