Verification Engine

Concept

A verification engine is the checking component in a verification workflow. In the TestRIG RISC-V CPU testing context, the concrete verification engine is QCVEngine, which uses Haskell QuickCheck with Direct Instruction Injection and RVFI traces to generate, compare, and shrink randomized instruction-sequence tests.

First seen 5/29/2026

Last seen 6/3/2026

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WIKI

Overview

A verification engine is the component that drives and evaluates tests or proof obligations against a correctness criterion. In the TestRIG RISC-V CPU-testing workflow, the verification engine is represented by QCVEngine, described as the “TestRIG Verification Engine.” QCVEngine leverages Haskell’s QuickCheck library to generate instruction sequences, compare execution traces, and shrink failing examples.

Role in TestRIG

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NEIGHBORHOOD

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RELATIONSHIPS

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QCVEngine ← implements 100% 4e

QCVEngine is an implementation of the Verification Engine concept in the TestRIG framework.

TestRIG ← depends on 100% 4e

TestRIG depends on a Verification Engine component to generate and compare instruction sequences.

LINKED ENTITIES

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QCVEngine IMPLEMENTS Extracted graph relationship

TestRIG DEPENDS_ON Extracted graph relationship

CITATIONS

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[1] QCVEngine is described as the TestRIG Verification Engine and uses Haskell QuickCheck. Randomized Testing of RISC-V CPUs using Direct

[2] DII decouples the instruction stream from control flow, enabling simplified generation and shrinking. Randomized Testing of RISC-V CPUs using Direct

[3] QCVEngine's QuickCheck function sends instruction lists over two DII sockets, collects RVFI traces, checks that they match, and returns a pass/fail result. Randomized Testing of RISC-V CPUs using Direct

[4] QCVEngine provides arbitrary and targeted instruction generators, including template-based generators for deeper states such as virtual-memory mappings and cache conflicts. Randomized Testing of RISC-V CPUs using Direct

[5] QCVEngine-supported replay can add full trace-equivalence checking with shrinking to recorded test-suite examples such as riscv-tests and RISCV-DV. Randomized Testing of RISC-V CPUs using Direct

[6] The TestRIG authors describe QCVEngine's initial generators as rudimentary and identify richer virtual-memory, cache, and floating-point generators as future work. Randomized Testing of RISC-V CPUs using Direct

[7] Future TestRIG memory-concurrency testing would require a more advanced verification engine that checks RVFI traces against higher-level memory-model semantics as well as equivalence. Randomized Testing of RISC-V CPUs using Direct

[8] The TestRIG repository collates TestRIG-compatible implementations and verification engines. Randomized Testing of RISC-V CPUs using Direct