Architectural Coverage

Concept

Architectural coverage is described in the TestRIG RISC-V randomized-testing evaluation as a first metric for basic verification. In that study, coverage was measured with sailcov by counting branches of the RISC-V Sail model explored during test runs, and was used to compare QCVEngine, riscv-tests, and RISCV-DV across selected RISC-V architecture configurations.

First seen 5/27/2026

Last seen 6/3/2026

Evidence 2 chunks

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WIKI

Definition

Architectural coverage is presented as the first metric for basic verification in a RISC-V CPU testing evaluation. In the cited study, it refers to coverage of the RISC-V architecture as observed through execution of the RISC-V Sail model. The tool sailcov measured this by recording how many branches of the RISC-V Sail model were explored during a run.

Use in RISC-V verification evaluation

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NEIGHBORHOOD

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RELATIONSHIPS

5 connections

QCVEngine ← evaluates 100% 7e

QCVEngine is used to evaluate architectural coverage of RISC-V implementations.

sailcov ← evaluates 100% 6e

sailcov is used to measure architectural coverage of RISC-V model branches.

TestRIG ← evaluates 95% 6e

TestRIG evaluates architectural coverage using sailcov to measure branch coverage of the Sail RISC-V model.

TestRIG ← uses 90% 2e

TestRIG evaluates architectural coverage as a metric for verification quality.

riscv-dv ← evaluates 85% 1e

RISCV-DV was evaluated for architectural coverage of RISC-V extensions.

LINKED ENTITIES

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TestRIG USES Extracted graph relationship

QCVEngine EVALUATES Extracted graph relationship

sailcov EVALUATES Extracted graph relationship

riscv-dv EVALUATES Extracted graph relationship

CITATIONS

10 sources

10 citations — click to expand

[1] Architectural coverage is the first metric for basic verification in the cited RISC-V testing evaluation. Randomized Testing of RISC-V CPUs using Direct

[2] sailcov measured architectural coverage by counting how many branches of the RISC-V Sail model were explored during a run. Randomized Testing of RISC-V CPUs using Direct

[3] The coverage study compared TestRIG QCVEngine against riscv-tests and RISCV-DV. Randomized Testing of RISC-V CPUs using Direct

[4] The study ran two runs of QCVEngine, riscv-tests, and RISCV-DV for RV32IMC and RV64IMAFDCZicsr. Randomized Testing of RISC-V CPUs using Direct

[5] For RV32IMC, the study measured Sail model coverage of I, M, and C extension instructions and general-purpose registers. Randomized Testing of RISC-V CPUs using Direct

[6] For RV64IMAFDCZicsr, the study measured coverage of I, M, A, F, D, C, and CSR instructions, as well as general-purpose and floating-point registers. Randomized Testing of RISC-V CPUs using Direct

[7] For riscv-tests, coverage was measured by running the test binaries on the Sail RISC-V model. Randomized Testing of RISC-V CPUs using Direct

[8] For RISCV-DV, the study produced TestRIG traces from Spike executing the tests and replayed them through RVFI-DII while measuring Sail RISC-V model coverage. Randomized Testing of RISC-V CPUs using Direct

[9] For QCVEngine, the study configured it with the two architecture strings and ran 500 sequences of each generator. Randomized Testing of RISC-V CPUs using Direct

[10] The RV32IMC results were similar across all three frameworks, which the authors said indicated QCVEngine could be a suitable alternative to unit and torture testing with respect to breadth of coverage. Randomized Testing of RISC-V CPUs using Direct