Architectural Coverage Wiki

Architectural Coverage

Concept WIKI v1 · 5/27/2026

Architectural coverage is described in the TestRIG RISC-V randomized-testing evaluation as a first metric for basic verification. In that study, coverage was measured with sailcov by counting branches of the RISC-V Sail model explored during test runs, and was used to compare QCVEngine, riscv-tests, and RISCV-DV across selected RISC-V architecture configurations.

Definition

Architectural coverage is presented as the first metric for basic verification in a RISC-V CPU testing evaluation. In the cited study, it refers to coverage of the RISC-V architecture as observed through execution of the RISC-V Sail model. The tool sailcov measured this by recording how many branches of the RISC-V Sail model were explored during a run.

Use in RISC-V verification evaluation

The coverage study compared the TestRIG QCVEngine against the RISC-V test suite, riscv-tests, and the RISCV-DV generator. The study used two runs of each framework for two architecture configurations:

RV32IMC
RV64IMAFDCZicsr

For RV32IMC, the study measured Sail model coverage for the I, M, and C extension instructions, as well as coverage of the general-purpose registers. For RV64IMAFDCZicsr, it measured coverage of I, M, A, F, D, C, and CSR instructions, plus coverage of general-purpose and floating-point registers.

Framework-specific measurement methods

The evaluation measured each framework through the Sail RISC-V model, but the measurement path differed by framework:

For riscv-tests, coverage was measured by running the test binaries on the Sail RISC-V model.
For RISCV-DV, the authors produced TestRIG traces from the Spike simulator executing the tests, then replayed those traces through RVFI-DII while measuring Sail model coverage.
For QCVEngine, the authors configured it with the two architecture strings and ran 500 sequences of each generator.

Reported interpretation

For RV32IMC, the results were reported as similar across QCVEngine, riscv-tests, and RISCV-DV. The authors interpreted this as indicating that QCVEngine can support a suitable alternative to unit testing and torture testing, at least with respect to breadth of coverage.

LINKED ENTITIES

4 links

CITATIONS

10 sources

10 citations

[1] Architectural coverage is the first metric for basic verification in the cited RISC-V testing evaluation. Randomized Testing of RISC-V CPUs using Direct

[2] sailcov measured architectural coverage by counting how many branches of the RISC-V Sail model were explored during a run. Randomized Testing of RISC-V CPUs using Direct

[3] The coverage study compared TestRIG QCVEngine against riscv-tests and RISCV-DV. Randomized Testing of RISC-V CPUs using Direct

[4] The study ran two runs of QCVEngine, riscv-tests, and RISCV-DV for RV32IMC and RV64IMAFDCZicsr. Randomized Testing of RISC-V CPUs using Direct

[5] For RV32IMC, the study measured Sail model coverage of I, M, and C extension instructions and general-purpose registers. Randomized Testing of RISC-V CPUs using Direct

[6] For RV64IMAFDCZicsr, the study measured coverage of I, M, A, F, D, C, and CSR instructions, as well as general-purpose and floating-point registers. Randomized Testing of RISC-V CPUs using Direct

[7] For riscv-tests, coverage was measured by running the test binaries on the Sail RISC-V model. Randomized Testing of RISC-V CPUs using Direct

[8] For RISCV-DV, the study produced TestRIG traces from Spike executing the tests and replayed them through RVFI-DII while measuring Sail RISC-V model coverage. Randomized Testing of RISC-V CPUs using Direct

[9] For QCVEngine, the study configured it with the two architecture strings and ran 500 sequences of each generator. Randomized Testing of RISC-V CPUs using Direct

[10] The RV32IMC results were similar across all three frameworks, which the authors said indicated QCVEngine could be a suitable alternative to unit and torture testing with respect to breadth of coverage. Randomized Testing of RISC-V CPUs using Direct